AD876 analog ground can lower the ac source impedance. The value 20 kHz. At a sample clock frequency of 20 MHz, the dc bias of this capacitance will depend on the source resistance and the current at 3 V dc is approximately 30 µA. If we choose R2 equal required signal bandwidth. to 1 kΩ and R1 equal to 50 Ω, the parallel capacitance should be a minimum of 0.008 µF to avoid attenuating signals close to The input span of the AD876 is a function of the reference 20 kHz. Note that the bias current will cause a 31.5 mV offset voltages. For more information regarding the input range, see from the 3 V bias. the DRIVING THE REFERENCE TERMINALS section of the data sheet. In systems that must use dc-coupling, use an op amp to level- shift a ground-referenced signal to comply with the input 3 requirements of the AD876. Figure 14 shows an AD817 AD876 configured in inverting mode with ac signal gain of –1. The dc 1 voltage at the noninverting input of the op amp controls the AIN2 amount of dc level shifting. A resistive voltage divider attenu- CCHP ates the REFBF signal. The op amp then multiplies the attenu- ated signal by 2. In the case where REFBF = 1.6 V, the dc output level will be 2.6 V. The AD817 is a low cost, fast settling, Figure 11. AD876 Equivalent Input Structure single supply op amp with a G = –1 bandwidth of 29 MHz. The AD818 is similar to the AD817 but has a 50 MHz bandwidth. < < 200 V Other appropriate op amps include the AD8011, AD812 (a dual), AIN and the AD8001. VSRf = 4.99k V +VCC0.1 m F Figure 12. Simple AD876 Drive Requirements AD876NC In many cases, particularly in single-supply operation, ac- coupling offers a convenient way of biasing the analog input 0Vdc2V p-pRIN = 4.99k V AD817 OR signal at the proper signal range. Figure 13 shows a typical AINAD8183k V configuration for ac-coupling the analog input signal to the REFBF AD876. Maintaining the specifications outlined in the data 14.7k V NC sheet requires careful selection of the component values. The most important concern is the f-3 dB high-pass corner that is a function of R2, and the parallel combination of C1 and C2. Figure 14. Bipolar Level Shift The f-3 dB point can be approximated by the equation An integrated difference amplifier such as the AD830 is an alternate means of providing dc level shifting. The AD830 f − = 1 3 dB provides a great deal of flexibility with control over offset and [2 × π × ( R2) Ceq ] gain. Figure 15 shows the AD830 precisely level-shifting a where Ceq is the parallel combination of C1 and C2. Note that unipolar, ground-referenced signal. The reference voltage, C1 is typically a large electrolytic or tantalum capacitor that REFBS, determines the amount of level-shifting. The ac gain becomes inductive at high frequencies. Adding a small ceramic is 1. The AD830 offers the advantages of high CMRR, precise or polystyrene capacitor on the order of 0.01 µF that does not gain, offset, and high-impedance inputs when compared with a become inductive until negligibly higher frequencies maintains discrete implementation. For more information regarding the a low impedance over a wide frequency range. AD830, see the AD830 data sheet. +12VAD8760.1C1R12VVVINAINB +2V0AD876R2VIBBC2AD830AIN3VVBIASVB0.1 Figure 13. AC-Coupled Inputs –12V There are additional considerations when choosing the resistor REFBS values. The ac-coupling capacitors integrate the switching transients present at the input of the AD876 and cause a net dc Figure 15. Level Shifting with the AD830 bias current, IB, to flow into the input. The magnitude of this bias current increases with increasing dc signal level and also REFERENCE INPUT DRIVING THE REFERENCE increases with sample frequency. This bias current will result in TERMINALS an offset error of (R1 + R2) × IB. If it is necessary to compen- The AD876 requires an external reference on pins REFTF and sate this error, consider making R2 negligibly small or modify- REFBF. The AD876 provides reference sense pins, REFTS ing VBIAS to account for the resultant offset. and REFBS, to minimize voltage drops caused by external and As an example, assume that the input to the AD876 must have internal wiring resistance. A resistor ladder, nominally 250 Ω, a dc bias of 3 V and the minimum expected signal frequency is connects pins REFTF and REFBF. –8– REV. B
