Datasheet AD7714 (Analog Devices) - 33

AD7714
interfaces which require control of the CS input on the AD7714, outputs from the ADSP-2103/ADSP-2105 are active. The serial one of the port bits of the 8XC51 (such as P1.1), which is con- clock rate on the ADSP-2103/ADSP-2105 should be limited to figured as an output, can be used to drive the CS input. 3␣ MHz to ensure correct operation with the AD7714.
DVDD DVDD SYNC SYNC RESET RESET RFS CS TFS POL AD7714 ADSP-2103/2105 AD7714 P3.0 DATA OUT DR DATA OUT 8XC51 DATA IN DT DATA IN P3.1 SCLK SCLK SCLK POL CS
Figure 11. AD7714 to ADSP-2103/ADSP-2105 Interface Figure 10. AD7714 to 8051 Interface
CODE FOR SETTING UP THE AD7714
The 8XC51 is configured in its Mode 0 serial interface mode. Table XV gives a set of read and write routines in C code for Its serial interface contains a single data line. As a result, the interfacing the 68HC11 microcontroller to the AD7714. The DATA OUT and DATA IN pins of the AD7714 should be sample program sets up the various registers on the AD7714 connected together. The serial clock on the 8XC51 idles high and reads 1000 samples from the part into the 68HC11. The between data transfers and, therefore, the POL input of the setup conditions on the part are exactly the same as those out- AD7714 should be hard-wired to a logic high. The 8XC51 lined for the flowchart of Figure 8. In the example code given outputs the LSB first in a write operation while the AD7714 here the DRDY output is polled to determine if a new valid expects the MSB first so the data to be transmitted has to be word is available in the output register. rearranged before being written to the output serial register. The sequence of the events in this program are as follows: Similarly, the AD7714 outputs the MSB first during a read operation while the 8XC51 expects the LSB first. Therefore, the 1. Write to the Communications Register, setting the channel. data that is read into the serial buffer needs to be rearranged 2. Write to the Filter High Register, setting the 4 MSBs of the before the correct data word from the AD7714 is available in filter word and setting the part for 24-bit read, bipolar mode the accumulator. with boost off.
AD7714 to ADSP-2103/ADSP-2105 Interface
3. Write to the Filter Low Register, setting the 8 LSBs of the Figure 11 shows an interface between the AD7714 and the filter word. ADSP-2103/ADSP-2105 DSP processor. In the interface shown, 4. Write to the Mode Register, setting the part for a gain of 1, the DRDY bit of the Communications Register is again moni- burnout current off, no filter synchronization and initiating a tored to determine when the Data Register is updated. The self-calibration. alternative scheme is to use an interrupt driven system in which case, the DRDY output is connected to the IRQ2 input of the 5. Poll the DRDY Output. ADSP-2103/ADSP-2105. The RFS and TFS pins of the 6. Read the data from the Data Register. ADSP-2103/ADSP-2105 are configured as active low outputs and the ADSP-2103/ADSP-2105 serial clock line, SCLK, is 7. Loop around doing steps 5 and 6 until the specified number also configured as an output. The POL pin of the AD7714 is of samples have been taken. hard-wired low. Because the SCLK from the ADSP-2103/ ADSP-2105 is a continuous clock, the CS of the AD7714 must be used to gate off the clock once the transfer is complete. The CS for the AD7714 is active when either the RFS or TFS –32– REV. C