Datasheet AD5686, AD5684 (Analog Devices) - 8

AD5686/AD5684 Data Sheet t1 SCLK 1 24 1 24 t3 t t 7 8 t4 t2 t t 10 8 SYNC t6 t5 SDIN DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ t9 t11 SDO DB23 DB0 HI-Z
005
SELECTED REGISTER DATA CLOCKED OUT
10797- Figure 5. Readback Timing Diagram Rev. C | Page 8 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER TRANSFER FUNCTION DAC ARCHITECTURE Output Amplifiers SERIAL INTERFACE Input Shift Register STANDALONE OPERATION WRITE AND UPDATE COMMANDS Write to Input Register n (Dependent on LDACB) Update DAC Register n with Contents of Input Register n Write to and Update DAC Channel n (Independent of LDACB) DAISY-CHAIN OPERATION READBACK OPERATION POWER-DOWN OPERATION LOAD DAC (HARDWARE LDACB PIN) Instantaneous DAC Updating (LDACB Held Low) Deferred DAC Updating (LDACB Is Pulsed Low) LDACB MASK REGISTER HARDWARE RESET (RESETB) RESET SELECT PIN (RSTSEL) APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING AD5686/AD5684 TO ADSP-BF531 INTERFACE AD5686/AD5684 TO SPORT INTERFACE LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE OUTLINE DIMENSIONS ORDERING GUIDE