Datasheet DAC8412, DAC8413 (Analog Devices) - 5

Data Sheet DAC8412/DAC8413 Parameter Symbol Conditions Min Typ Max Units
Write Data Setup tWDS tWCS = 150 ns 20 ns Write Data Hold tWDH tWCS = 150 ns 0 ns Load Data Pulse Width tLDW 180 ns Reset Pulse Width tRESET 150 ns Chip Select Read Pulse Width tRCS 170 ns Read Data Hold tRDH tRCS = 170 ns 20 ns Read Data Setup tRDS tRCS = 170 ns 0 ns Data to High-Z tDZ CL = 10 pF 200 ns Chip Select to Data tCSD CL = 100 pF 320 ns SUPPLY CHARACTERISTICS Power Supply Sensitivity PSS 100 ppm/V Positive Supply Current IDD 7 12 mA Negative Supply Current ISS VSS = −5.0 V −10 mA Power Dissipation PDISS VSS = 0 V 60 mW VSS = −5.0 V 110 mW 1 All supplies can be varied ±5%, and operation is guaranteed. Device is tested with VDD = 4.75 V. 2 For single-supply operation only (VREFL = 0.0 V, VSS = 0.0 V). Due to internal offset errors, INL and DNL are measured beginning at 0x005. 3 Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 4 All parameters are guaranteed by design. 5 All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
tWCS CS tWS tWH R/W t t AS AH tRDS A0/A1 CS t t RCS RDH t tLH tLDW LS R/W LDAC tAS tAH t t WDS WDH A0/A1 DATA IN tDZ DATA HIGH-Z HIGH-Z t DATA VALID
3
RESET OUT
00 04 0 4-
RESET
4-
t
27
CSD
27 00 00 Figure 3. Data Output (Read Timing) Figure 4. Data Write (Input and Output Registers) Timing Rev. G | Page 5 of 20 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Introduction DACs Glitch Reference Inputs Digital I/O Coding Supplies Amplifiers Reference Configurations Single +5 V Supply Operation Outline Dimensions Ordering Guide