link to page 4 ADL5205Data SheetPin No.MnemonicDescription 14 LATCHB Latch B. A logic low on this pin allows the gain to change on Channel B in parallel gain control interface mode. A logic high on this pin prevents gain changes. 15 VINB− Channel B Negative Analog Input. 16 VINB+ Channel B Positive Analog Input. 17 PWUPB Channel B Power-Up. A logic high on this pin powers up Channel B, and a logic low on this pin disables it. 18 VCMB Channel B Common-Mode Output. 21 VOUTB− Channel B Negative Analog Output. 22 VOUTB+ Channel B Positive Analog Output. 24, 27 VPOS Positive Power Supply. 29 VOUTA+ Channel A Negative Analog Output. 30 VOUTA− Channel A Positive Output. 33 VCMA Channel A Common-Mode Output. 34 PWUPA Channel A Power-Up. A logic high on this pin powers up Channel A, and a logic low on this pin disables it. 35 VINA+ Channel A Positive Analog Input. 36 VINA− Channel A Negative Analog Input. 37 LATCHA Latch A. A logic low on this pin allows the gain to change on Channel A in the parallel gain control interface mode. A logic high on this pin prevents gain changes. 38 UPDN_DAT_A/A0 Data Pin for the Channel A Up/Down Function (UPDN_DAT_A). Bit 0 for Channel A in Parallel Gain Control Interface Mode (A0). 39 UPDN_CLK_A/A1 Clock Interface for the Channel A Up/Down Function (UPD_CLK_A). Bit 1 for Channel A in Parallel Gain Control Interface Mode (A1). 40 FA_A/A2 Fast Attack for Channel A (FA_A). In serial mode, a logic high on this pin attenuates Channel A according to an FA SPI word. Bit 2 for Channel A in Parallel Gain Control Interface (A2). EP GND Exposed Pad Ground. The exposed pad must be connected to a low impedance ground plane. This is the ground (0 V) reference for all the voltages in Table 1. Rev. 0 | Page 8 of 31 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE JUNCTION TO BOARD THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC STRUCTURE CONTROL/LOGIC CIRCUITRY COMMON-MODE VOLTAGE APPLICATIONS INFORMATION BASIC CONNECTIONS DIGITAL INTERFACE OVERVIEW Parallel Digital Interface Serial Peripheral Interface (SPI) Up/Down Interface SPI READ ADC INTERFACING NOISE FIGURE vs. GAIN SETTING EVALUATION BOARD OVERVIEW POWER SUPPLY INTERFACE SIGNAL INPUTS AND OUTPUTS MANUAL CONTROLS Mode Switches Channel Control Switches PARALLEL INTERFACE SERIAL INTERFACE STANDARD DEVELOPMENT PLATFORM (SDP) INTERFACE EVALUATION BOARD CONTROL SOFTWARE COMMAND LINE CONTROL PROGRAM GRAPHICAL USER INTERFACE (GUI) PROGRAM EVALUATION BOARD SCHEMATICS AND LAYOUT BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE
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