Datasheet AD8253 (Analog Devices)

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10 MHz, 20 V/μs, G = 1, 10, 100, 1000
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CMOS Programmable Gain Instrumentation Amplifier Data Sheet AD8253 FEATURES FUNCTIONAL BLOCK DIAGRAM Small package: 10-lead MSOP DGND WR A1 A0 2 6 5 4 Programmable gains: 1, 10, 100, 1000 Digital or pin-programmable gain setting LOGIC –IN 1 Wide supply: ±5 V to ±15 V Excellent dc performance High CMRR: 100 dB (minimum), G = 100 7 OUT Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.2 μV/°C (maximum), G = 1000 Excellent ac performance +IN 10 Fast settling time: 780 ns to 0.001% (maximum) AD8253 High slew rate: 20 V/μs (minimum) Low distortion: −110 dB THD at 1 kHz,10 V swing 8 3 9
01 0 3-
+V
98
High CMRR over frequency: 100 dB to 20 kHz (minimum) S –VS REF
06
Low noise: 10 nV/√Hz, G = 1000 (maximum)
Figure 1.
Low power: 4 mA 80 APPLICATIONS 70 G = 1000 60 Data acquisition Biomedical analysis 50 G = 100 Test and measurement ) 40 B d ( GENERAL DESCRIPTION 30 IN G = 10 GA 20
The AD8253 is an instrumentation amplifier with digitally programmable gains that has gigaohm (GΩ) input impedance,
10 G = 1
low output noise, and low distortion, making it suitable for
0
interfacing with sensors and driving high sample rate analog-to-
–10
digital converters (ADCs).
–20
23
1k 10k 100k 1M 10M 100M
-0 It has a high bandwidth of 10 MHz, low THD of −110 dB, and 83
FREQUENCY (Hz)
69 00 fast settling time of 780 ns (maximum) to 0.001%. Offset drift and Figure 2. Gain vs. Frequency gain drift are guaranteed to 1.2 μV/°C and 10 ppm/°C, respectively, for G = 1000. In addition to its wide input common voltage range,
Table 1. Instrumentation Amplifiers by Category
it boasts a high common-mode rejection of 100 dB at G = 1000
General Zero Mil Low High Speed Purpose Drift Grade Power PGA
from dc to 20 kHz. The combination of precision dc performance AD82201 AD82311 AD620 AD6271 AD8250 coupled with high speed capabilities makes the AD8253 an excellent candidate for data acquisition. Furthermore, this AD8221 AD85531 AD621 AD6231 AD8251 monolithic solution simplifies design and manufacturing and AD8222 AD85551 AD524 AD82231 AD8253 boosts performance of instrumentation by maintaining a tight AD82241 AD85561 AD526 match of internal resistors and amplifiers. AD8228 AD85571 AD624 The AD8253 user interface consists of a parallel port that allows 1 Rail-to-rail output. users to set the gain in one of two different ways (see Figure 1 The AD8253 is available in a 10-lead MSOP package and is for the functional block diagram). A 2-bit word sent via a bus specified over the −40°C to +85°C temperature range, making it can be latched using the WR input. An alternative is to use an excellent solution for applications where size and packing transparent gain mode, where the state of logic levels at the gain density are important considerations. port determines the gain.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN SELECTION Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode POWER SUPPLY REGULATION AND BYPASSING INPUT BIAS CURRENT RETURN PATH INPUT PROTECTION REFERENCE TERMINAL COMMON-MODE INPUT VOLTAGE RANGE LAYOUT Grounding Coupling Noise Common-Mode Rejection RF INTERFERENCE DRIVING AN ANALOG-TO-DIGITAL CONVERTER APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT SETTING GAINS WITH A MICROCONTROLLER DATA ACQUISITION OUTLINE DIMENSIONS ORDERING GUIDE