Datasheet AD8363 (Analog Devices) - 27

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AD8363 Data Sheet EVALUATION AND CHARACTERIZATION CIRCUIT BOARD LAYOUTS
Figure 57 to Figure 61 show the evaluation board for the AD8363.
VTGT VREF VPOS C7 0.1µF R7 VPOS 0Ω R8 R14 0Ω 0Ω C5 R11 R10 100pF 1.4kΩ 845Ω 12 11 10 9 VSET TEMP S EF M TGT M V VR VPO R2 CO OPEN R13 VOUT OPEN C10 13 8 C11 NC TEMP 0.1µF OPEN 14 7 R6 R15 IN INHI VSET AD8363 R1 0Ω 0Ω 15 6 0Ω INLO DUT1 VOUT VOUT C6 C12 16 5 OPEN TCM1 0.1µF TCM1 CLPF DN C9 W P 0.1µF R17 2/ F S M R18 OPEN M OPEN CM R5 C8 T CHP VPO CO OPEN 0Ω 1 2 3 4 VREFC PADDLE AGND TCM2/PWDN C3 C4 OPEN 100pF GND GNDI R12 R9 R16 C13 OPEN OPEN 0Ω 0.1µF VPOSC
074
VREFC VPOS1
07368- Figure 57. Evaluation Board Schematic Rev. B | Page 26 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE CHOICE OF RF INPUT PIN SMALL SIGNAL LOOP RESPONSE TEMPERATURE SENSOR INTERFACE VREF INTERFACE TEMPERATURE COMPENSATION INTERFACE POWER-DOWN INTERFACE VSET INTERFACE OUTPUT INTERFACE VTGT INTERFACE MEASUREMENT MODE BASIC CONNECTIONS SYSTEM CALIBRATION AND ERROR CALCULATION OPERATION TO 125°C OUTPUT VOLTAGE SCALING OFFSET COMPENSATION, MINIMUM CLPF, AND MAXIMUM CHPF CAPACITANCE VALUES CHOOSING A VALUE FOR CLPF RF PULSE RESPONSE AND VTGT CONTROLLER MODE BASIC CONNECTIONS CONSTANT OUTPUT POWER OPERATION DESCRIPTION OF RF CHARACTERIZATION EVALUATION AND CHARACTERIZATION CIRCUIT BOARD LAYOUTS ASSEMBLY DRAWINGS OUTLINE DIMENSIONS ORDERING GUIDE