Datasheet LTC6905 (Analog Devices) - 7

LTC6905
THEORY OF OPERATION
As shown in the Block Diagram, the LTC6905’s master highest frequency range, with the master output frequency oscillator is controlled by the ratio of the voltage between passed directly to OUT. The DIV pin may be fl oated or driven the V+ and SET pins and the current entering the SET pin to midsupply to select ÷2, the intermediate frequency (IRES). The voltage on the SET pin is forced to approxi- range. The lowest frequency range, ÷4, is selected by mately 1V below V+ by the PMOS transistor and its gate tying DIV to GND or driving it below 0.5V. Figure 1 shows bias voltage. the relationship between RSET , divider setting and output frequency, including the overlapping frequencies. A resistor RSET , connected between the V+ and SET pins, “locks together” the voltage (V+ – V 30 SET) and current, IRES, variation. This provides the LTC6905’s high precision. The master oscillation frequency reduces to: 25 ÷4 ÷2 ÷1 168. MHz 5 • 1 k 0 Ω 20 f = + 1. MHz MO 5 (Ω) R SET SETR 15 To extend the output frequency range, the master oscillator signal is divided by 1, 2 or 4 before driving OUT (Pin 5). 10 The LTC6905 is optimized for use with resistors between 10k and 25k, corresponding to oscillator frequencies 510 60 110 160 between 17.225MHz and 170MHz. The divide-by value is OUTPUT FREQUENCY (MHz) determined by the state of the DIV input (Pin 4). Tie DIV to 6905 F01 V+ or drive it to within 0.4V of V+ to select ÷1. This is the
Figure 1. RSET vs Output Frequency
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