Datasheet LTC6909 (Analog Devices) - 7

LTC6909
block DiAgrAM
PH0 PH1 PH2 V+D 3 4 15 13 I f MASTER MASTER = 20MHz • 10k • = 20MHz • 10k/RSET V+ – V (SSFM = OFF) SET V+A MASTER DRIVER 5 OUT1 1 + OSCILLATOR RSET V DRIVER 6 OUT2 VSET 16 – OUT SET DRIVER 7 OUT3 V+ – V 1 POLE OUTPUT I SET SET = IMASTER V LPF PHASING BIAS RSET DRIVER 8 OUT4 DRIVERS DRIVER 9 OUT5 IREF DRIVER 10 OUT6 MDAC DRIVER 11 OUT7 DRIVER 12 OUT8 V+ OUTPUT PSEUDORANDOM Hi-Z + CODE GENERATOR – UNTIL POR STABLE DIVIDE BY MOD 3-STATE 14 16/32/64 INPUT DECODER DETECT WHEN A CLOCK SIGNAL IS PRESENT AT THE + CLOCK INPUT MOD PIN INPUT, THE MODULATION IS DISABLED – GND 2 GND 6909 BD 6909fa 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts