Datasheet LTC4418 (Linear Technology) - 9

LTC4418
BLOCK DIAGRAM
INTVCC 3.2µA INTVCC V SHDN OUT + V1 V2 1V – DISABLE GATEDRIVERS AND RESET VALIDATION TIMER INTVCC INTVCC REGULATOR 3.2µA 20µA INTVCC EN + INTVCC 1V – DISABLE GATEDRIVERS CAS TMR HYS GND HYSTERESIS OSCILLATOR IEXT EXT HYS UV1 PRIORITIZED + NONOVERLAP – CONTROL UV LOGIC UV2 INT HYS IEXT UV 1.03V VALIDATION CH1 1V TIMER VALID 120mV INTV 970mV CC + +– HOLD REV VOUT OV CH OFF V1 I – EXT V2 OV + OV1 VS1 – + EXTERNAL VGS SWITCH ON – +– OV2 VS2 6.2V 300mV G1 VALID1 GATE G2 DRIVER VALID2 CHANNEL 1 CHANNEL 2 4418 BD 4418f For more information www.linear.com/LTC4418 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts