Datasheet MCP606, MCP607, MCP608 (Microchip) - 18

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MCP606/7/8/9
4.8.2 PHOTODIODE AMPLIFIERS operate at a much higher speed. This reverse bias also increases the dark current and current noise, however. Sensors that produce an output current and have high Resistor R output impedance can be connected to a 2 converts the current into voltage. Capacitor C transimpedance amplifier. The transimpedance 2 limits the bandwidth and helps stabilize the circuit when D amplifier converts the current into voltage. Photodiodes 1’s junction capacitance is large. are one sensor that produce an output current. V < 0 The key op amp characteristics that are needed for B V = I R these circuits are: low input offset voltage, low input OUT D1 2 bias current, high input impedance and an input common mode range that includes ground. The low C2 input offset voltage and low input bias current support a very low voltage drop across the photodiode; this gives the best photodiode linearity. Since the R2 photodiode is biased at ground, the op amp’s input VOUT ID1 needs to function well both above and below ground. Light VDD 4.8.2.1 Photo-Voltaic Mode D
MCP606
Figure 4-9 shows a transimpedance amplifier with a 1 photodiode (D1) biased in the Photo-voltaic mode (0V across D1), which is used for precision photodiode VB sensing. As light impinges on D1, charge is generated, causing
FIGURE 4-10:
Photodiode (in Photo- a current to flow in the reverse bias direction of D1. The conductive mode) and Transimpedance op amp’s negative feedback forces the voltage across Amplifier. the D1 to be nearly 0V. Resistor R2 converts the current into voltage. Capacitor C2 limits the bandwidth and 4.8.3 TWO OP AMP INSTRUMENTATION helps stabilize the circuit when D1’s junction AMPLIFIER capacitance is large. The two op amp instrumentation amplifier shown in Figure 4-11 serves the function of taking the difference V = I R OUT D1 2 of two input voltages, level-shifting it and gaining it to the output. This configuration is best suited for higher C2 gains (i.e., gain > 3 V/V). The reference voltage (VREF) is typically at mid-supply (VDD/2) in a single-supply environment. R2 VOUT ID1 ⎛ R 2R ⎞ Light VDD 1 1 V = (V – V ) 1 ⎜ + --- + ----- ⎟ + V OUT 1 2 ⎝ R R ⎠ REF 2 G D1
MCP606
RG R R 1 2 R R 2 1 VREF VOUT
FIGURE 4-9:
Photodiode (in Photo-voltaic mode) and Transimpedance Amplifier. V2
½ ½ MCP607 MCP607
4.8.2.2 Photo-Conductive Mode V1 Figure 4-9 shows a transimpedance amplifier with a photodiode (D1) biased in the Photo-conductive mode
FIGURE 4-11:
Two Op Amp (D1 is reverse biased), which is used for high-speed Instrumentation Amplifier. applications. The key specifications that make the MCP606/7/8/9 As light impinges on D1, charge is generated, causing family appropriate for this application circuit are low a current to flow in the reverse bias direction of D1. input bias current, low offset voltage and high Placing a negative bias on D1 significantly reduces its common-mode rejection. junction capacitance, which allows the circuit to DS11177F-page 18 © 2009 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the CS Pin on the MCP608. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage at VDD = 5.5V. FIGURE 2-2: Input Offset Voltage at VDD = 2.5V. FIGURE 2-3: Quiescent Current vs. Power Supply Voltage. FIGURE 2-4: Input Offset Voltage Drift Magnitude at VDD = 5.5V. FIGURE 2-5: Input Offset Voltage Drift Magnitude at VDD = 2.5V. FIGURE 2-6: Quiescent Current vs. Ambient Temperature. FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature. FIGURE 2-8: Open-Loop Gain and Phase vs. Frequency. FIGURE 2-9: Channel-to-Channel Separation (MCP607 and MCP609 only). FIGURE 2-10: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-11: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-12: Input Noise Voltage Density vs. Frequency. FIGURE 2-13: Input Bias Current, Input Offset Current vs. Ambient Temperature. FIGURE 2-14: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-15: CMRR, PSRR vs. Frequency. FIGURE 2-16: Input Bias Current, Input Offset Current vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-18: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-19: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-20: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-21: Slew Rate vs. Ambient Temperature. FIGURE 2-22: Output Voltage Headroom vs. Ambient Temperature at RL = 5 kW. FIGURE 2-23: The MCP606/7/8/9 Show No Phase Reversal. FIGURE 2-24: Output Short Circuit Current Magnitude vs. Ambient Temperature. FIGURE 2-25: Large-signal, Non-inverting Pulse Response. FIGURE 2-26: Small-signal, Non-inverting Pulse Response. FIGURE 2-27: Chip Select (CS) Hysteresis (MCP608 only). FIGURE 2-28: Large-signal, Inverting Pulse Response. FIGURE 2-29: Small-signal, Inverting Pulse Response. FIGURE 2-30: Amplifier Output Response Times vs. Chip Select (CS) Pulse (MCP608 only). FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Unity Gain Buffer has a Limited VOUT Range. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 MCP608 Chip Select 4.5 Supply Bypass 4.6 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.7 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.8 Application Circuits FIGURE 4-8: Low Side Battery Current Sensor. FIGURE 4-9: Photodiode (in Photo-voltaic mode) and Transimpedance Amplifier. FIGURE 4-10: Photodiode (in Photo- conductive mode) and Transimpedance Amplifier. FIGURE 4-11: Two Op Amp Instrumentation Amplifier. FIGURE 4-12: Three Op Amp Instrumentation Amplifier. FIGURE 4-13: Precision Gain with Good Load Isolation. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information