Datasheet Summary SAM D21E, SAM D21G, SAM D21J (Microchip) - 8

32-bit ARM-Based Microcontrollers 3. Ordering Information
SAMD 21 E 15 A - M U T Product Family Package Carrier SAMD = General Purpose Microcontroller No character = Tray (Default) T = Tape and Reel Product Series 21 = Cortex M0 + CPU, Basic Feature Set + DMA + USB Package Grade U = -40 - 85OC Matte Sn Plating Pin Count F = -40 - 125 E = 32 Pins (35 Pins for WLCSP) OC Matte Sn Plating G = 48 Pins (45 Pins for WLCSP) J = 64 Pins Package Type Flash Memory Density A = TQFP 18 = 256KB M = QFN 17 = 128KB U = WLCSP 16 = 64KB C = UFBGA 15 = 32KB Device Variant A = Default Variant B = Added RWW support for 32KB and 64KB memory options C = Silicon revision F for WLCSP35 package option.
3.1 SAM D21E Table 3-1. Device Variant A Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type
ATSAMD21E15A-AU 32K 4K TQFP32 Tray ATSAMD21E15A-AUT Tape & Reel ATSAMD21E15A-AF Tray ATSAMD21E15A-AFT Tape & Reel ATSAMD21E15A-MU QFN32 Tray ATSAMD21E15A-MUT Tape & Reel ATSAMD21E15A-MF Tray ATSAMD21E15A-MFT Tape & Reel © 2017 Microchip Technology Inc.
Datasheet Summary
40001884A-page 8 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 3.1. SAM D21E 3.2. SAM D21G 3.3. SAM D21J 3.4. Device Identification 4. Block Diagram 5. Pinout 5.1. SAM D21J 5.1.1. QFN64 / TQFP64 5.1.2. UFBGA64 5.2. SAM D21G 5.2.1. QFN48 / TQFP48 5.2.2. WLCSP45 5.3. SAM D21E 5.3.1. QFN32 / TQFP32 5.3.2. WLCSP35 6. Product Mapping 7. Processor And Architecture 7.1. Cortex M0+ Processor 7.1.1. Cortex M0+ Configuration 7.1.2. Cortex-M0+ Peripherals 7.1.3. Cortex-M0+ Address Map 7.1.4. I/O Interface 7.1.4.1. Overview 7.1.4.2. Description 7.2. Nested Vector Interrupt Controller 7.2.1. Overview 7.2.2. Interrupt Line Mapping 7.3. Micro Trace Buffer 7.3.1. Features 7.3.2. Overview 7.4. High-Speed Bus System 7.4.1. Features 7.4.2. Configuration 7.4.3. SRAM Quality of Service 7.5. AHB-APB Bridge 7.6. PAC - Peripheral Access Controller 7.6.1. Overview 7.6.2. Register Description 7.6.2.1. PAC0 Register Description 7.6.2.1.1. Write Protect Clear 7.6.2.1.2. Write Protect Set 7.6.2.2. PAC1 Register Description 7.6.2.2.1. Write Protect Clear 7.6.2.2.2. Write Protect Set 7.6.2.3. PAC2 Register Description 7.6.2.3.1. Write Protect Clear 7.6.2.3.2. Write Protect Set 8. Packaging Information 8.1. Thermal Considerations 8.1.1. Thermal Resistance Data 8.1.2. Junction Temperature 8.2. Package Drawings 8.2.1. 64 pin TQFP 8.2.2. 64 pin QFN 8.2.3. 64-ball UFBGA 8.2.4. 48 pin TQFP 8.2.5. 48 pin QFN 8.2.6. 45-ball WLCSP 8.2.7. 32 pin TQFP 8.2.8. 32 pin QFN 8.2.9. 35 ball WLCSP (Device Variant B) 8.2.10. 35 ball WLCSP (Device Variant C) 8.3. Soldering Profile The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service