Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 8ATtiny24A/44A/84A 8183FS–AVR–06/12 Document Outline Features 1. Pin Configurations 1.1 Pin Descriptions 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB3:PB0) 1.1.4 RESET 1.1.5 Port A (PA7:PA0) 2. Overview 3. General Information 3.1 Resources 3.2 Code Examples 3.3 Capacitive Touch Sensing 3.4 Data Retention 3.5 Disclaimer 4. Register Summary 5. Instruction Set Summary 6. Ordering Information 6.1 ATtiny24A 6.2 ATtiny44A 6.3 ATtiny84A 7. Packaging Information 7.1 14S1 7.2 14P3 7.3 15CC1 7.4 20M1 7.5 20M2 8. Errata 8.1 ATtiny24A 8.1.1 Rev. H 8.1.2 Rev. G 8.1.3 Rev. F 8.2 ATtiny44A 8.2.1 Rev. G 8.2.2 Rev. F 8.2.3 Rev. E 8.3 ATtiny84A 8.3.1 Rev. C 9. Datasheet Revision History 9.1 Rev. 8183F – 06/12 9.2 Rev. 8183E – 01/12 9.3 Rev. 8183D – 04/11 9.4 Rev. 8183C – 03/11 9.5 Rev. 8183B – 03/10 9.6 Rev. 8183A – 12/08
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