Datasheet ATmega64A - Summary (Microchip) - 7

4. Block Diagram Figure 4-1 Block Diagram SRAM
TCK
CPU
TMS
JTAG
OCD TDI
FLASH
TDO
PARPROG NVM
PEN
programming EEPROM
PDI
EEPROMIF SERPROG
PDO SCK AD[7:0]
ExtMem
A[15:8]
Clock generation
RD/WR/ALE
D
XTAL1
8MHz 8MHz Power A Crystal Osc Calib RC management
PA[7:0]
T
PB[7:0] XTAL2
12MHz A External and clock External I/O
PC[7:0]
B clock RC Osc control
PD[7:0] TOSC1
U PORTS
PE[7:0]
32.768kHz S
PF[7:0]
1MHz int
PG[4:0]
XOSC osc
TOSC2
ExtInt
INT[7:0] VCC
Power Watchdog Supervision Timer
RESET
ADC
ADC[7:0]
POR/BOD &
AREF GND
RESET Internal
AIN0
Reference AC
AIN1 ACO ADCMUX MISO MOSI
SPI TC 0
SCK (8-bit async) OC0 SS OC1A/B/C SDA
TWI TC 1
T1 SCL (16-bit) ICP1 RxD0
TC 2
T2 TxD0
USART 0
(8-bit) OC2 XCK0 RxD1
TC 3
OC3A/B TxD1
USART 1
(16-bit) T3 XCK1 ICP3 Atmel ATmega64A [DATASHEET] 7 Atmel-8160ES-8-bit AVR Micrcontroller_Datasheet_Summary-09/2015 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 4. Block Diagram 5. ATmega103 and ATmega64A Compatibility 5.1. ATmega103 Compatibility Mode 6. Pin Configurations 6.1. Pin Descriptions 6.1.1. VCC 6.1.2. GND 6.1.3. Port A (PA7:PA0) 6.1.4. Port B (PB7:PB0) 6.1.5. Port C (PC7:PC0) 6.1.6. Port D (PD7:PD0) 6.1.7. Port E (PE7:PE0) 6.1.8. Port F (PF7:PF0) 6.1.9. Port G (PG4:PG0) 6.1.10. RESET 6.1.11. XTAL1 6.1.12. XTAL2 6.1.13. AVCC 6.1.14. AREF 6.1.15. PEN 7. Resources 8. Data Retention 9. About Code Examples 10. Capacitive Touch Sensing 11. Packaging Information 11.1. 64A 11.2. 64M1 12. Errata 12.1. ATmega64A Rev. D