Datasheet Complete ATtiny48, ATtiny88 (Atmel) - 5

ATtiny48/88 2. Overview
The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power con- sumption versus processing speed.
2.1 Block Diagram Figure 2-1.
Block Diagram C GND VC Watchdog Power debugWIRE Timer Supervision POR / BOD & Watchdog Program RESET Oscillator Logic Oscillator Flash SRAM Circuits / Clock Generation CPU EEPROM 8bit T/C 0 16bit T/C 1 A/D Conv. 2 6 TABUS A Internal D Bandgap Analog SPI TWI Comp. PORT D (8) PORT B (8) PORT C (8) PORT A (4) RESET CLKI PD[0:7] PB[0:7] PC[0:7] PA[0:3] (in TQFP and MLF) The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers.
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8008H–AVR–04/11 Document Outline Features 1. Pin Configurations 1.1 Pin Descriptions 1.1.1 VCC 1.1.2 AVCC 1.1.3 GND 1.1.4 Port A (PA3:0) 1.1.5 Port B (PB7:0) 1.1.6 Port C (PC7, PC5:0) 1.1.7 PC6/RESET 1.1.8 Port D (PD7:0) 2. Overview 2.1 Block Diagram 2.2 Comparison Between ATtiny48 and ATtiny88 3. General Information 3.1 Resources 3.2 About Code Examples 3.3 Capacitive Touch Sensing 3.4 Data Retention 3.5 Disclaimer 4. AVR CPU Core 4.1 Introduction 4.2 Architectural Overview 4.3 ALU – Arithmetic Logic Unit 4.4 Status Register 4.5 General Purpose Register File 4.5.1 The X-register, Y-register, and Z-register 4.6 Stack Pointer 4.7 Instruction Execution Timing 4.8 Reset and Interrupt Handling 4.8.1 Interrupt Response Time 4.9 Register Description 4.9.1 SPH and SPL — Stack Pointer Registers 4.9.2 SREG – Status Register 5. Memories 5.1 Program Memory (Flash) 5.2 Data Memory (SRAM) and Register Files 5.2.1 General Purpose Register File 5.2.2 I/O Register File 5.2.3 Extended I/O Register File 5.2.4 Data Memory (SRAM) 5.3 Data Memory (EEPROM) 5.3.1 Programming Methods 5.3.2 Read 5.3.3 Erase 5.3.4 Write 5.3.5 Preventing EEPROM Corruption 5.3.6 Program Examples 5.4 Register Description 5.4.1 EEARH and EEARL – EEPROM Address Register 5.4.2 EEDR – EEPROM Data Register 5.4.3 EECR – EEPROM Control Register 5.4.4 GPIOR2 – General Purpose I/O Register 2 5.4.5 GPIOR1 – General Purpose I/O Register 1 5.4.6 GPIOR0 – General Purpose I/O Register 0 6. Clock System 6.1 Clock Subsystems 6.1.1 CPU Clock – clkCPU 6.1.2 I/O Clock – clkI/O 6.1.3 Flash Clock – clkFLASH 6.1.4 Analog to Digital Converter Clock – clkADC 6.1.5 High-Speed Two-Wire Interface Clock – clkTWIHS 6.2 Clock Sources 6.2.1 External Clock 6.2.2 Calibrated Internal 8MHz Oscillator 6.2.3 Internal 128 kHz Oscillator 6.2.4 Default Clock Source 6.3 System Clock Prescaler 6.3.1 Switching Prescaler Setting 6.4 Clock Output Buffer 6.5 Clock Startup Sequence 6.6 Register Description 6.6.1 OSCCAL – Oscillator Calibration Register 6.6.2 CLKPR – Clock Prescale Register 7. Power Management and Sleep Modes 7.1 Sleep Modes 7.1.1 Idle Mode 7.1.2 ADC Noise Reduction Mode 7.1.3 Power-Down Mode 7.2 Software BOD Disable 7.3 Minimizing Power Consumption 7.3.1 Analog to Digital Converter 7.3.2 Analog Comparator 7.3.3 Brown-Out Detector 7.3.4 Internal Voltage Reference 7.3.5 Watchdog Timer 7.3.6 Port Pins 7.3.7 On-chip Debug System 7.4 Register Description 7.4.1 SMCR – Sleep Mode Control Register 7.4.2 MCUCR – MCU Control Register 7.4.3 PRR – Power Reduction Register 8. System Control and Reset 8.1 Resetting the AVR 8.2 Reset Sources 8.2.1 Power-on Reset 8.2.2 External Reset 8.2.3 Brown-Out Detection 8.2.4 Watchdog Reset 8.3 Internal Voltage Reference 8.3.1 Voltage Reference Enable Signals and Start-up Time 8.4 Watchdog Timer 8.5 Register Description 8.5.1 MCUSR – MCU Status Register 8.5.2 WDTCSR – Watchdog Timer Control Register 9. Interrupts 9.1 Interrupt Vectors 9.2 External Interrupts 9.2.1 Pin Change Interrupt Timing 9.2.2 Low Level Interrupt 9.3 Register Description 9.3.1 EICRA – External Interrupt Control Register A 9.3.2 EIMSK – External Interrupt Mask Register 9.3.3 EIFR – External Interrupt Flag Register 9.3.4 PCICR – Pin Change Interrupt Control Register 9.3.5 PCIFR – Pin Change Interrupt Flag Register 9.3.6 PCMSK3 – Pin Change Mask Register 3 9.3.7 PCMSK2 – Pin Change Mask Register 2 9.3.8 PCMSK1 – Pin Change Mask Register 1 9.3.9 PCMSK0 – Pin Change Mask Register 0 10. I/O-Ports 10.1 Introduction 10.2 Ports as General Digital I/O 10.2.1 Configuring the Pin 10.2.2 Toggling the Pin 10.2.3 Break-Before-Make Switching 10.2.4 Switching Between Input and Output 10.2.5 Reading the Pin Value 10.2.6 Digital Input Enable and Sleep Modes 10.2.7 Unconnected Pins 10.3 Alternate Port Functions 10.3.1 Alternate Functions of Port A 10.3.2 Alternate Functions of Port B 10.3.3 Alternate Functions of Port C 10.3.4 Alternate Functions of Port D 10.4 Register Description 10.4.1 MCUCR – MCU Control Register 10.4.2 PORTCR – Port Control Register 10.4.3 PORTA – The Port A Data Register 10.4.4 DDRA – The Port A Data Direction Register 10.4.5 PINA – The Port A Input Pins 10.4.6 PORTB – The Port B Data Register 10.4.7 DDRB – The Port B Data Direction Register 10.4.8 PINB – The Port B Input Pins 10.4.9 PORTC – The Port C Data Register 10.4.10 DDRC – The Port C Data Direction Register 10.4.11 PINC – The Port C Input Pins 10.4.12 PORTD – The Port D Data Register 10.4.13 DDRD – The Port D Data Direction Register 10.4.14 PIND – The Port D Input Pins 11. 8-bit Timer/Counter0 11.1 Features 11.2 Overview 11.2.1 Definitions 11.2.2 Registers 11.3 Timer/Counter Clock Sources 11.4 Counter Unit 11.5 Output Compare Unit 11.5.1 Compare Match Blocking by TCNT0 Write 11.5.2 Using the Output Compare Unit 11.6 Modes of Operation 11.6.1 Normal Mode 11.6.2 Clear Timer on Compare Match (CTC) Mode 11.7 Timer/Counter Timing Diagrams 11.8 8-bit Timer/Counter Register Description 11.8.1 TCCR0A – Timer/Counter Control Register A 11.8.2 TCNT0 – Timer/Counter Register 11.8.3 OCR0A – Output Compare Register A 11.8.4 OCR0B – Output Compare Register B 11.8.5 TIMSK0 – Timer/Counter Interrupt Mask Register 11.8.6 TIFR0 – Timer/Counter 0 Interrupt Flag Register 12. 16-bit Timer/Counter1 with PWM 12.1 Features 12.2 Overview 12.2.1 Registers 12.2.2 Definitions 12.3 Accessing 16-bit Registers 12.3.1 Reusing the Temporary High Byte Register 12.4 Timer/Counter Clock Sources 12.5 Counter Unit 12.6 Input Capture Unit 12.6.1 Input Capture Trigger Source 12.6.2 Noise Canceler 12.6.3 Using the Input Capture Unit 12.7 Output Compare Units 12.7.1 Force Output Compare 12.7.2 Compare Match Blocking by TCNT1 Write 12.7.3 Using the Output Compare Unit 12.8 Compare Match Output Unit 12.8.1 Compare Output Mode and Waveform Generation 12.9 Modes of Operation 12.9.1 Normal Mode 12.9.2 Clear Timer on Compare Match (CTC) Mode 12.9.3 Fast PWM Mode 12.9.4 Phase Correct PWM Mode 12.9.5 Phase and Frequency Correct PWM Mode 12.10 Timer/Counter Timing Diagrams 12.11 Register Description 12.11.1 TCCR1A – Timer/Counter1 Control Register A 12.11.2 TCCR1B – Timer/Counter1 Control Register B 12.11.3 TCCR1C – Timer/Counter1 Control Register C 12.11.4 TCNT1H and TCNT1L – Timer/Counter1 12.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A 12.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B 12.11.7 ICR1H and ICR1L – Input Capture Register 1 12.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register 12.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register 13. Timer/Counter0 and Timer/Counter1 Prescalers 13.1 Internal Clock Source 13.2 Prescaler Reset 13.3 External Clock Source 13.4 Register Description 13.4.1 GTCCR – General Timer/Counter Control Register 14. SPI – Serial Peripheral Interface 14.1 Features 14.2 Overview 14.3 SS Pin Functionality 14.3.1 Slave Mode 14.3.2 Master Mode 14.4 Data Modes 14.5 Register Description 14.5.1 SPCR – SPI Control Register 14.5.2 SPSR – SPI Status Register 14.5.3 SPDR – SPI Data Register 15. TWI – Two Wire Interface 15.1 Features 15.2 Overview 15.3 Bus Definitions 15.3.1 TWI Terminology 15.3.2 Electrical Interconnection 15.4 Data Transfer and Frame Format 15.4.1 Transferring Bits 15.4.2 START and STOP Conditions 15.4.3 Address Packet Format 15.4.4 Data Packet Format 15.4.5 Combining Address and Data Packets into a Transmission 15.5 Multi-master Bus Systems, Arbitration and Synchronization 15.6 Overview of the TWI Module 15.6.1 SCL and SDA Pins 15.6.2 Bit Rate Generator Unit 15.6.3 Bus Interface Unit 15.6.4 Address Match Unit 15.6.5 Control Unit 15.7 Using the TWI 15.8 Transmission Modes 15.8.1 Master Transmitter Mode 15.8.2 Master Receiver Mode 15.8.3 Slave Receiver Mode 15.8.4 Slave Transmitter Mode 15.8.5 Miscellaneous States 15.8.6 Combining Several TWI Modes 15.9 Multi-master Systems and Arbitration 15.10 Compatibility with SMBus 15.11 Register Description 15.11.1 TWBR – TWI Bit Rate Register 15.11.2 TWCR – TWI Control Register 15.11.3 TWSR – TWI Status Register 15.11.4 TWDR – TWI Data Register 15.11.5 TWAR – TWI (Slave) Address Register 15.11.6 TWAMR – TWI (Slave) Address Mask Register 15.11.7 TWHSR – TWI High Speed Register 16. Analog Comparator 16.1 Analog Comparator Multiplexed Input 16.2 Register Description 16.2.1 ADCSRB – ADC Control and Status Register B 16.2.2 ACSR – Analog Comparator Control and Status Register 16.2.3 DIDR1 – Digital Input Disable Register 1 17. ADC – Analog to Digital Converter 17.1 Features 17.2 Overview 17.3 Operation 17.4 Starting a Conversion 17.5 Prescaling and Conversion Timing 17.6 Changing Channel or Reference Selection 17.6.1 ADC Input Channels 17.6.2 ADC Voltage Reference 17.7 ADC Noise Canceler 17.8 Analog Input Circuitry 17.9 Analog Noise Canceling Techniques 17.10 ADC Accuracy Definitions 17.11 ADC Conversion Result 17.12 Temperature Measurement 17.13 Register Description 17.13.1 ADMUX – ADC Multiplexer Selection Register 17.13.2 ADCSRA – ADC Control and Status Register A 17.13.3 ADCL and ADCH – The ADC Data Register 17.13.3.1 ADLAR = 0 17.13.3.2 ADLAR = 1 17.13.4 ADCSRB – ADC Control and Status Register B 17.13.5 DIDR0 – Digital Input Disable Register 0 18. debugWIRE On-Chip Debug System 18.1 Features 18.2 Overview 18.3 Physical Interface 18.4 Software Break Points 18.5 Limitations of debugWIRE 18.6 Register Description 18.6.1 DWDR – debugWire Data Register 19. Self-Programming the Flash 19.0.1 Performing Page Erase by SPM 19.0.2 Filling the Temporary Buffer (Page Loading) 19.0.3 Performing a Page Write 19.1 Addressing the Flash During Self-Programming 19.1.1 EEPROM Write Prevents Writing to SPMCSR 19.1.2 Reading the Fuse and Lock Bits from Software 19.1.3 Preventing Flash Corruption 19.1.4 Programming Time for Flash when Using SPM 19.2 Register Description 19.2.1 SPMCSR – Store Program Memory Control and Status Register 20. Lock Bits, Fuse Bits and Device Signature 20.1 Lock Bits 20.2 Fuse Bits 20.2.1 Latching of Fuses 20.3 Signature Bytes 20.4 Calibration Byte 21. External Programming 21.1 Memory Parametrics 21.2 Parallel Programming 21.2.1 Enter Programming Mode 21.2.2 Considerations for Efficient Programming 21.2.3 Chip Erase 21.2.4 Programming the Flash 21.2.5 Programming the EEPROM 21.2.6 Reading the Flash 21.2.7 Reading the EEPROM 21.2.8 Programming Low Fuse Bits 21.2.9 Programming High Fuse Bits 21.2.10 Programming Extended Fuse Bits 21.2.11 Programming the Lock Bits 21.2.12 Reading Fuse and Lock Bits 21.2.13 Reading Signature Bytes 21.2.14 Reading the Calibration Byte 21.3 Serial Programming 21.3.1 Pin Mapping 21.3.2 Programming Algorithm 21.3.3 Programming Instruction set 21.4 Programming Time for Flash and EEPROM 22. Electrical Characteristics 22.1 Absolute Maximum Ratings* 22.2 DC Characteristics 22.3 Speed 22.4 Clock Characterizations 22.4.1 Calibrated Internal Oscillator Accuracy 22.4.2 External Clock Drive 22.5 System and Reset Characterizations 22.6 Analog Comparator Characteristics 22.7 ADC Characteristics 22.8 Two-Wire Serial Interface Characteristics 22.9 SPI Characteristics 22.10 Parallel Programming Characteristics 22.11 Serial Programming Characteristics 23. Typical Characteristics 23.1 ATtiny48 23.1.1 Current Consumption in Active Mode 23.1.2 Current Consumption in Idle Mode 23.1.3 Current Consumption in Power-down Mode 23.1.4 Current Consumption in Reset 23.1.5 Current Consumption in Peripheral Units 23.1.6 Pull-up Resistors 23.1.7 Output Driver Strength 23.1.8 Input Threshold and Hysteresis 23.1.9 BOD, Bandgap and Reset 23.1.10 Internal Oscillator Speed 23.2 ATtiny88 23.2.1 Current Consumption in Active Mode 23.2.2 Current Consumption in Idle Mode 23.2.3 Current Consumption in Power-down Mode 23.2.4 Current Consumption in Reset 23.2.5 Current Consumption in Peripheral Units 23.2.6 Pull-up Resistors 23.2.7 Output Driver Strength 23.2.8 Input Threshold and Hysteresis 23.2.9 BOD, Bandgap and Reset 23.2.10 Internal Oscillator Speed 24. Register Summary 25. Instruction Set Summary 26. Ordering Information 26.1 ATtiny48 26.2 ATtiny88 27. Packaging Information 27.1 28M1 27.2 28P3 27.3 32A 27.4 32CC1 27.5 32M1-A 28. Errata 28.1 ATtiny48 28.1.1 Rev. C 28.1.2 Rev. B 28.1.3 Rev. A 28.2 ATtiny88 28.2.1 Rev. C 28.2.2 Rev. B 28.2.3 Rev. A 29. Datasheet Revision History 29.1 Rev. 8008H - 04/11 29.2 Rev. 8008G - 04/11 29.3 Rev. 8008F - 06/10 29.4 Rev. 8008E - 05/10 29.5 Rev. 8008D - 03/10 29.6 Rev. 8008C - 03/09 29.7 Rev. 8008B - 06/08 29.8 Rev. 8008A - 06/08 Table of Contents