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Datasheet MCP41XXX/42XXX (Microchip)

ОписаниеSingle/Dual Digital Potentiometer with SPI Interface
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MCP41XXX/42XXX. Single/Dual Digital Potentiometer with SPI™ Interface. Features. Description. Block Diagram. Package Types

Datasheet MCP41XXX/42XXX Microchip, Версия: 04-06-2004

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MCP41XXX/42XXX Single/Dual Digital Potentiometer with SPI™ Interface Features Description
• 256 taps for each potentiometer The MCP41XXX and MCP42XXX devices are 256- • Potentiometer values for 10 kΩ, 50 kΩ and position, digital potentiometers available in 10 kΩ, 100 kΩ 50 kΩ and 100 kΩ resistance versions. The • Single and dual versions MCP41XXX is a single-channel device and is offered in an 8-pin PDIP or SOIC package. The MCP42XXX con- • SPI™ serial interface (mode 0,0 and 1,1) tains two independent channels in a 14-pin PDIP, SOIC • ±1 LSB max INL & DNL or TSSOP package. The wiper position of the • Low power CMOS technology MCP41XXX/42XXX varies linearly and is controlled via • 1 µA maximum supply current in static operation an industry-standard SPI interface. The devices con- • Multiple devices can be daisy-chained together sume <1 µA during static operation. A software shut- (MCP42XXX only) down feature is provided that disconnects the “A” terminal from the resistor stack and simultaneously con- • Shutdown feature open circuits of all resistors for maximum power savings nects the wiper to the “B” terminal. In addition, the dual MCP42XXX has a SHDN pin that performs the same • Hardware shutdown pin available on MCP42XXX function in hardware. During shutdown mode, the con- only tents of the wiper register can be changed and the • Single supply operation (2.7V - 5.5V) potentiometer returns from shutdown to the new value. • Industrial temperature range: -40°C to +85°C The wiper is reset to the mid-scale position (80h) upon • Extended temperature range: -40°C to +125°C power-up. The RS (reset) pin implements a hardware reset and also returns the wiper to mid-scale. The
Block Diagram
MCP42XXX SPI interface includes both the SI and SO pins, allowing daisy-chaining of multiple devices. Chan- RS SHDN nel-to-channel resistance matching on the MCP42XXX varies by less than 1%. These devices operate from a VDD single 2.7 - 5.5V supply and are specified over the VSS PB0 extended and industrial temperature ranges. Resistor Wiper Control Register Array 0 Logic
Package Types
1 8 V 16-Bit Wiper Resistor PA1
DD Register Array 1
* P
SI Shift PW1 SCK 2
7 PB0 Register
SI 3 6 PW0 SCK VSS 4 5 PA0 S0
Potentiometer P1 is only available on the dual MCP42XXX version.
CS 1 14 VDD
SCK 2 13 SO SI 3 12 SHDN V 4 11 RS SS PB1 5 10 PB0 PW1 6 9 PW0 PA1 7 8 PA0 2003 Microchip Technology Inc. DS11195C-page 1 Document Outline 1.0 Electrical Characteristics Figure 1-1: Detailed Serial interface Timing. Figure 1-2: Reset Timing. Figure 1-3: Software Shutdown Exit Timing. 2.0 Typical Performance Curves Figure 2-1: Normalized Wiper to End Terminal Resistance vs. Code. Figure 2-2: Potentiometer INL Error vs. Code. Figure 2-3: Potentiometer Mode Tempco vs. Code. Figure 2-4: Nominal Resistance 10kW vs. Temperature. Figure 2-5: Nominal Resistance 50kW vs. Temperature. Figure 2-6: Nominal Resistance 100kW vs. Temperature. Figure 2-7: Rheostat INL Error vs. Code. Figure 2-8: Rheostat Mode Tempco vs. Code. Figure 2-9: Static Current vs. Temperature. Figure 2-10: Active Supply Current vs. Temperature. Figure 2-11: Active Supply Current vs. Clock Frequency. Figure 2-12: Reset & Shutdown Pins Current vs. Voltage. Figure 2-13: 10kW Device Wiper Resistance Histogram. Figure 2-14: 50kW, 100kW Device Wiper Resistance Histogram. Figure 2-15: One Position Settling Time. Figure 2-16: Full-Scale Settling Time. Figure 2-17: Digital Feed through vs. Time. Figure 2-18: Gain vs. Frequency for 10kW Potentiometer. Figure 2-19: Gain vs. Frequency for 50kW Potentiometer. Figure 2-20: Gain vs. Frequency for 100kW Potentiometer. Figure 2-21: -3 dB Bandwidths. Figure 2-22: Power Supply Rejection Ratio vs. Frequency. Figure 2-23: 10kW Wiper Resistance vs. Voltage. Figure 2-24: 50kW & 100kW Wiper Resistance vs. Voltage. 2.1 Parametric Test Circuits Figure 2-25: Potentiometer Divider Non- Linearity Error Test Circuit (DNL, INL). Figure 2-26: Resistor Position Non- Linearity Error Test Circuit (Rheostat operation DNL, INL). Figure 2-27: Wiper Resistance Test Circuit. Figure 2-28: Power Supply Sensitivity Test Circuit (PSS, PSRR). Figure 2-29: Gain vs. Frequency Test Circuit. Figure 2-30: Capacitance Test Circuit. 3.0 Pin Descriptions 3.1 PA0, PA1 3.2 PB0, PB1 3.3 PW0, PW1 3.4 Chip Select (CS) 3.5 Serial Clock (SCK) 3.6 Serial Data Input (SI) 3.7 Serial Data Output (SO) (MCP42XXX devices only) 3.8 Reset (RS) (MCP42XXX devices only) 3.9 Shutdown (SHDN) (MCP42XXX devices only) Table 3-1: MCP41XXX Pins Table 3-2: MCP42XXX Pins 4.0 Applications Information Figure 4-1: Block diagram showing the MCP42XXX dual digital potentiometer. Data register 0 and da... 4.1 Modes of Operation Figure 4-2: Two-terminal or rheostat configuration for the digital potentiometer. Acting as a res... Figure 4-3: Three terminal or voltage divider mode. 4.2 Typical Applications Figure 4-4: Single-supply, programmable, inverting gain amplifier using a digital potentiometer. Figure 4-5: Single-supply, programmable, non-inverting gain amplifier. Figure 4-6: Gain vs. Code for inverting and differential amplifier circuits. Figure 4-7: Single Supply programmable differential amplifier using digital potentiometers. Figure 4-8: By changing the values of R1 and R2, the voltage output resolution of this programmab... 4.3 Calculating Resistances Figure 4-9: Potentiometer resistances are a function of code. It should be noted that, when using... Figure 4-10: Example Resistance calculations. 5.0 Serial Interface 5.1 Command Byte 5.2 Writing Data Into Data Registers 5.3 Using The Shutdown Command Figure 5-1: Timing Diagram for Writing Instructions or Data to a Digital Potentiometer. Figure 5-2: Command Byte Format. 5.4 Daisy-Chain Configuration Figure 5-3: Timing Diagram for Daisy-Chain Configuration. Figure 5-4: Daisy-Chain Configuration. 5.5 Reset (RS) Pin Operation 5.6 Shutdown (SHDN) Pin Operation 5.7 Power-up Considerations Table 5-1: Truth Table for Logic Inputs 5.8 Using the MCP41XXX/42XXX in SPI Mode 1,1 Figure 5-5: Timing Diagram for SPI Mode 1,1 Operation. 6.0 Packaging Information 6.1 Package Marking Information
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