Datasheet LTC4307-1 (Analog Devices) - 3

LTC4307-1
The ELECTRICAL CHARACTERISTICS
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denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VTHR_ENABLE ENABLE Threshold 0.8 1.4 2 V IENABLE ENABLE Input Current ENABLE from 0V to VCC ● 0.1 ±5 μA tPLH_EN ENABLE Delay Off-On VCC = 3.3V (Figure 1) 95 μs tPHL_EN ENABLE Delay On-Off VCC = 3.3V (Note 3) (Figure 1) 10 ns tPLH_READY READY Delay Off-On VCC = 3.3V (Note 3) (Figure 1) 10 ns tPHL_READY READY Delay On-Off VCC = 3.3V (Note 3) (Figure 1) 10 ns VOL_READY READY Output Low Voltage IPULLUP = 3mA, VCC = 2.3V ● 0.4 V IOFF_READY READY Off Leakage Current VCC = READY = 5.5V ● 0.1 ±5 μA
Propagation Delay
tPHL SDA/SCL Propagation Delay High to Low CLOAD = 50pF, 2.7k to VCC on SDA, SCL, 70 ns VCC = 3.3V (Notes 2, 3) (Figure 1) tPLH SDA/SCL Propagation Delay Low to High CLOAD = 50pF, 2.7k to VCC on SDA, SCL, 10 ns VCC = 3.3V (Notes 2, 3) (Figure 1) tFALL SDA/SCL Transition Time High to Low CLOAD = 100pF, 10k to VCC on SDA, SCL, 30 300 ns VCC = 3.3V (Notes 3, 4) (Figure 1)
Input-Output Connection
VOS Input-Output Offset Voltage 2.7k to VCC on SDA, SCL, VCC = 3.3V, ● 20 60 100 mV Driven SDA, SCL = 0.2V VTHR SDA, SCL Logic Input Threshold Voltage Rising Edge 0.45VCC 0.55VCC 0.65VCC V VHYS SDA, SCL Logic Input Threshold Voltage (Note 3) 50 mV Hysteresis CIN Digital Input Capacitance SDAIN, SDAOUT, (Note 3) 10 pF SCLIN, SCLOUT ILEAK Input Leakage Current SDA, SCL, Pins ● ±5 μA VOL Output Low Voltage SDA, SCL Pins, ISINK = 4mA, ● 0 0.4 V SDAIN/SCLIN = 0.2V, VCC = 2.7V 2.7k to VCC on SDA, SCL, VCC = 3.3V, ● 120 160 205 mV Driven SDA, SCL = 0.1V VILMAX Buffer Input Logic Low Voltage VCC = 3.3V ● 1.2 V
Timing Characteristics
fI2C,MAX I2C Maximum Operating Frequency (Note 3) 400 600 kHz tBUF Bus Free Time Between Stop and Start (Note 3) 1.3 μs Condition tHD,STA Hold Time After (Repeated) Start Condition (Note 3) 100 ns tSU,STA Repeated Start Condition Set-Up Time (Note 3) 0 ns tSU,STO Stop Condition Set-Up Time (Note 3) 0 ns tHD,DATI Data Hold Time Input (Note 3) 0 ns tSU,DAT Data Set-Up Time (Note 3) 100 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 3:
Determined by design, not tested in production. may cause permanent damage to the device. Exposure to any Absolute
Note 4:
Measure points are 0.3 • VCC and 0.7 • VCC. Maximum Rating condition for extended periods may affect device
Note 5:
ICC test performed with connection circuitry active. reliability and lifetime.
Note 6:
All currents into pins are positive; all voltages are referenced to
Note 2:
See “Propagation Delays” in the Operations section for a GND unless otherwise specifi ed. discussion of tPHL and tPLH as a function of pull-up resistance and bus capacitance. 43071fa 3