Datasheet ICL7106, ICL7107, ICL7107S (Intersil) - 9

link to page 9 link to page 9 link to page 9 ICL7106, ICL7107, ICL7107S
a a a a f b f b f b g c g g e c e c e c b d d d 7 7 7 SEGMENT SEGMENT SEGMENT DECODE DECODE DECODE TYPICAL SEGMENT OUTPUT V+ LATCH 0.5mA TO 1000’s 100’s 10’s 1’s SEGMENT COUNTER COUNTER COUNTER COUNTER 8mA TO SWITCH DRIVERS DIGITAL GROUND FROM COMPARATOR OUTPUT 1 V+ V+ CLOCK TEST †

4 LOGIC CONTROL 37 500Ω DIGITAL † THREE INVERTERS GROUND 27 ONE INVERTER SHOWN FOR CLARITY 40 39 38 OSC 1 OSC 2 OSC 3
FIGURE 8. ICL7107 DIGITAL SECTION System Timing
INTERNAL TO PART
Figure 9 shows the clocking arrangement used in the ICL7106 and ICL7107. Two basic clocking arrangements can be used: 
4 CLOCK
1. Figure 9A. An external oscillator connected to pin 40. 2. Figure 9B. An R-C oscillator using all three pins. The oscillator frequency is divided by four before it clocks the
40 39 38
decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference deintegrate (0 to 2000 counts) and auto-zero (1000 to
GND ICL7107 TEST ICL7106
3000 counts). For signals less than full scale, auto-zero gets the FIGURE 9A. unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used.
INTERNAL TO PART
 To achieve maximum rejection of 60Hz pickup, the signal
4 CLOCK
integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 331/3kHz, etc., should be selected. For 50Hz rejection, oscillator frequencies of 200kHz, 100kHz, 662/3kHz, 50kHz, 40kHz, etc.,
40 39 38
would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz).
R C RC OSCILLATOR
FIGURE 9B. FIGURE 9. CLOCK CIRCUITS FN3082 Rev 9.00 Page 9 of 17 October 24, 2014