Datasheet ADXL343 (Analog Devices) - 32

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Data Sheet ADXL343 NOISE PERFORMANCE 10k X-AXIS
The specification of noise shown in Table 1 corresponds to
Y-AXIS
the typical noise performance of the ADXL343 in normal power
Z-AXIS
operation with an output data rate of 100 Hz (LOW_POWER bit
) g µ ( 1k
(D4) = 0, rate bits (D3:D0) = 0xA in the BW_RATE register, Address 0x2C). For normal power operation at data rates below
TION IA V
100 Hz, the noise of the ADXL343 is equivalent to the noise at 100 Hz ODR in LSBs. For data rates greater than 100 Hz, the
AN DE L 100
noise increases roughly by a factor of √2 per doubling of the data
AL
rate. For example, at 400 Hz ODR, the noise on the x- and y-axes is typically less than 1.5 LSB rms, and the noise on the z-axis is typically less than 2.2 LSB rms.
10 0.01 0.1 1 10 100 1k 10k
251 For low power operation (LOW_POWER bit (D4) = 1 in the
AVERAGING PERIOD, (s)
10627- BW_RATE register, Address 0x2C), the noise of the ADXL343 Figure 42. Root Allan Deviation is constant for all valid data rates shown in Table 8. This value is
130
typically less than 1.8 LSB rms for the x- and y-axes and typically
)
less than 2.6LSB rms for the z-axis.
% ( E 120
The trend of noise performance for both normal power and low
OIS N X-AXIS
power modes of operation of the ADXL343 is shown in Figure 41.
D 110 Y-AXIS LIZE Z-AXIS
Figure 42 shows the typical Al an deviation for the ADXL343.
A M
The 1/f corner of the device, as shown in this figure, is very low,
100 OR
al owing absolute resolution of approximately 100 µg (assuming
OF N
that there is sufficient integration time). Figure 42 also shows
90 GE A
that the noise density is 290 µg/√Hz for the x-axis and y-axis
T EN
and 430 µg/√Hz for the z-axis.
C 80 PER
Figure 43 shows the typical noise performance trend of the
70
ADXL343 over supply voltage. The performance is normalized
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
252 to the tested and specified supply voltage, V
SUPPLY VOLTAGE, VS (V)
S = 2.5 V. In general, 10627- noise decreases as supply voltage is increased. It should be noted, as Figure 43. Normalized Noise vs. Supply Voltage, VS shown in Figure 41, that the noise on the z-axis is typical y higher
OPERATION AT VOLTAGES OTHER THAN 2.5 V
than on the x-axis and y-axis; therefore, while they change roughly The ADXL343 is tested and specified at a supply voltage of the same in percentage over supply voltage, the magnitude of change V on the z-axis is greater than the magnitude of change on the S = 2.5 V; however, it can be powered with VS as high as 3.6 V or as low as 2.0 V. Some performance parameters change as the x-axis and y-axis. supply voltage changes: offset, sensitivity, noise, self-test, and
5.0
supply current.
4.5 X-AXIS, LOW POWER Y-AXIS, LOW POWER
Due to slight changes in the electrostatic forces as supply voltage
Z-AXIS, LOW POWER 4.0 X-AXIS, NORMAL POWER
is varied, the offset and sensitivity change slightly. When operating
Y-AXIS, NORMAL POWER 3.5 Z-AXIS, NORMAL POWER
at a supply voltage of VS = 3.3 V, the x- and y-axis offset is typical y
B rms) S 3.0 L
25 mg higher than at Vs = 2.5 V operation. The z-axis is typical y
( E IS 2.5
20 mg lower when operating at a supply voltage of 3.3 V than when
NO
operating at V
2.0
S = 2.5 V. Sensitivity on the x- and y-axes typically
UT P
shifts from a nominal 256 LSB/g (ful -resolution or ±2 g, 10-bit
1.5 UT O
operation) at VS = 2.5 V operation to 265 LSB/g when operating
1.0
with a supply voltage of 3.3 V. The z-axis sensitivity is unaffected by
0.5
a change in supply voltage and is the same at VS = 3.3 V operation
0
as it is at VS = 2.5 V operation. Simple linear interpolation can be
3.13 6.25 12.50 25 50 100 200 400 800 1600 3200
250 used to determine typical shifts in offset and sensitivity at other
OUTPUT DATA RATE (Hz)
10627- Figure 41. Noise vs. Output Data Rate for Normal and Low Power Modes, supply voltages. Full-Resolution (256 LSB/g) Rev. 0 | Page 31 of 36 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Package Information ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Power Savings Power Modes Auto Sleep Mode Standby Mode Serial Communications SPI Preventing Bus Traffic Errors I2C Interrupts DATA_READY SINGLE_TAP DOUBLE_TAP Activity Inactivity FREE_FALL Watermark Overrun FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO Self-Test Register Map Register Definitions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Tap Detection Threshold Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Using Self-Test Data Formatting of Upper Data Rates Noise Performance Operation at Voltages Other Than 2.5 V Offset Performance at Lowest Data Rates Axes of Acceleration Sensitivity Layout and Design Recommendations Outline Dimensions Ordering Guide