Datasheet ADIS16467 (Analog Devices) - 7

ADIS16467 Preliminary Technical Data t2 tSTDR t1 SYNC DR
4 0 0 7-
t
43
NV
5 1 Figure 4. Input Clock Timing Diagram, Pulse Sync Mode, Register MSC_CTRL, Bits[4:2] = 101 (Binary)
tSTDR 2 t1 SYNC DR
5 0 0 7-
tNV
543 1 Figure 5. Input Clock Timing Diagram, Direct Sync Mode, Register MSC_CTRL, Bits[4:2] = 001 (Binary) Rev. PrA | Page 6 of 33