Datasheet LT1160, LT1162 (Analog Devices) - 6

LT1160/LT1162
U U U PIN FUNCTIONS LT1160 LT1162 SV+ (Pin 1):
Main Signal Supply. Must be closely decoupled
SV+ (Pins 1, 7):
Main Signal Supply. Must be closely to the signal ground Pin 5. decoupled to ground Pins 5 and 11.
IN TOP (Pin 2):
Top Driver Input. Pin 2 is disabled when Pin
IN TOP (Pins 2, 8):
Top Driver Input. The Input Top is 3 is high. A 3k input resistor followed by a 5V internal disabled when the Input Bottom is high. A 3k input resistor clamp prevents saturation of the input transistors. followed by a 5V internal clamp prevents saturation of the input transistors.
IN BOTTOM (Pin 3):
Bottom Driver Input. Pin 3 is disabled when Pin 2 is high. A 3k input resistor followed by a 5V
IN BOTTOM (Pins 3, 9):
Bottom Driver Input. The Input internal clamp prevents saturation of the input transistors. Bottom is disabled when the Input Top is high. A 3k input resistor followed by a 5V internal clamp prevents satura-
UV OUT (Pin 4):
Undervoltage Output. Open collector NPN tion of the input transistors. output which turns on when V + drops below the undervoltage threshold.
UV OUT (Pins 4, 10):
Undervoltage Output. Open collector NPN output which turns on when V+ drops below the
SGND (Pin 5):
Small Signal Ground. Must be routed undervoltage threshold. separately from other grounds to the system ground.
GND (Pins 5, 11):
Ground Connection.
PGND (Pin 6):
Bottom Driver Power Ground. Connects to source of bottom N-channel MOSFET.
B GATE FB (Pins 6, 12):
Bottom Gate Feedback. Must connect directly to the bottom power MOSFET gate. The
B GATE FB (Pin 8):
Bottom Gate Feedback. Must connect top MOSFET turn-on is inhibited until Bottom Gate Feed- directly to the bottom power MOSFET gate. The top back pins have discharged to below 2.5V. MOSFET turn-on is inhibited until Pin 8 has discharged to below 2.5V.
B GATE DR (Pins 13, 19):
Bottom Gate Drive. The high current drive point for the bottom MOSFET. When a gate
B GATE DR (Pin 9):
Bottom Gate Drive. The high current resistor is used it is inserted between the Bottom Gate drive point for the bottom MOSFET. When a gate resistor Drive pin and the gate of the MOSFET. is used it is inserted between Pin 9 and the gate of the MOSFET.
PV+ (Pins 14, 20):
Bottom Driver Supply. Must be con- nected to the same supply as Pins 1 and 7.
PV+ (Pin 10):
Bottom Driver Supply. Must be connected to the same supply as Pin 1.
T SOURCE (Pins 15, 21):
Top Driver Return. Connects to the top MOSFET source and the low side of the bootstrap
T SOURCE (Pin 11):
Top Driver Return. Connects to the capacitor. top MOSFET source and the low side of the bootstrap capacitor.
T GATE FB (Pins 16, 22):
Top Gate Feedback. Must connect directly to the top power MOSFET gate. The
T GATE FB (Pin 12):
Top Gate Feedback. Must connect bottom MOSFET turn-on is inhibited until VTGF – VTSOURCE directly to the top power MOSFET gate. The bottom has discharged to below 2.9V. MOSFET turn-on is inhibited until V12 – V11 has discharged to below 2.9V.
T GATE DR (Pins 17, 23):
Top Gate Drive. The high current drive point for the top MOSFET. When a gate resistor is
T GATE DR (Pin 13):
Top Gate Drive. The high current drive used it is inserted between the Top Gate Drive pin and the point for the top MOSFET. When a gate resistor is used it gate of the MOSFET. is inserted between Pin 13 and the gate of the MOSFET.
BOOST (Pins 18, 24):
Top Driver Supply. Connects to the
BOOST (Pin 14):
Top Driver Supply. Connects to the high high side of the bootstrap capacitor. side of the bootstrap capacitor. 11602fb 6