TABLE I. Electrical performance characteristics. Conditions 1/ 2/ 3/ Test Symbol -55°C ≤ TA ≤ +125°C Group A Device Limits Unit unless otherwise specified subgroups type Min Max DC performance section Input offset voltage VOS 1 All 5.5 mV M, D, P, L, R 1 01 6.5 M, D, P, L 1 02 6.5 2,3 All 9.0 Positive input bias current +IIB 1 All -6 +6 µA M, D, P, L, R 1 01 -10 10 M, D, P, L 1 02 -10 10 2,3 All -12 +12 Negative input bias current -IIB 1 All -25 +25 µA M, D, P, L, R 1 01 -25 +25 M, D, P, L 1 02 -25 +25 2,3 All -35 +35 Open loop transresistance ROLT VOUT = ±2.5 V 4 All 250 kΩ 4/ 5,6 175 Input characteristics section Common mode rejection CMRR VCM = ±2.5 V 1 All 50 dB ratio 4/ 2,3 47 Output characteristics section Output voltage swing 4/ VOUT RL = 150 Ω 1 All -2.7 +2.7 V 2,3 -2.6 +2.6 Output current 4/ IOUT RL = 37.5 Ω, TA = +25°C 1 All 50 mA Short circuit current 4/ IOS TA = +25°C 1 All 85 mA Power supply section Power supply operating 4/ VPS 1,2,3 All ±3 ±6 V range Quiescent current IQ 1 All 5.5 mA M, D, P, L, R 1 01 5.5 M, D, P, L 1 02 5.5 2,3 All 6.0 Power supply rejection PSRR +V 1,2,3 All 60 dB S = +4 V to +6 V, ratio -VS = -5 V 4/ -VS = -4 V to –6 V, 1 50 +VS = +5 V 2,3 47 See footnotes at end of table. STANDARD SIZE 5962-94593MICROCIRCUIT DRAWINGA DLA LAND AND MARITIME REVISION LEVEL SHEET COLUMBUS, OHIO 43218-3990 E 5 DSCC FORM 2234 APR 97 Document Outline DEPARTMENT OF DEFENSE SPECIFICATION DEPARTMENT OF DEFENSE STANDARDS
