TABLE I. Electrical performance characteristics. Conditions 1/ Test Symbol -55°C ≤ TA ≤ +125°C Group A Device Limits 2/ Unit unless otherwise specified subgroups type Min Max Input offset voltage VOS VS = ±5 V, VCM = 0 V 1 01 ±2.0 mV 2,3 ±4.0 VS = ±15 V, VCM = 0 V 1 ±2.0 2,3 ±5.0 Input bias current IIB VS = ±5 V and ±15 V, 1 01 7.0 µA VCM = 0 V 2,3 9.5 Input offset current IOS VS = ±5 V and ±15 V, 1 01 0.3 µA VCM = 0 V 2,3 0.4 Output current 3/ I 4 01 16 mA OUT VS = ±5 V, VOUT = ±2.5 V, TA = +25°C V 20 S = ±15 V, VOUT = ±10 V, TA = +25°C Common mode input 4/ VCM VS = ±5 V 1,2,3 01 ±2.5 V voltage range VS = ±15 V ±12 Quiescent power IQ VS = ±5 V, VOUT = 0 V 1 01 13 mA supply current 2,3 17.5 VS = ±15 V, VOUT = 0 V 1 13.5 2,3 18 Quiescent power 5/ PQ VS = ±5 V, VOUT = 0 V, 1 01 130 mW consumption IOUT = 0 mA 2,3 175 VS = ±15 V, VOUT = 0 V, 1 405 IOUT = 0 mA 2,3 540 Power supply rejection PSRR VS = ±5 V to ±15 V 1 01 75 dB ratio 2,3 72 Open loop gain AOL VS = ±5 V, RL = 500 Ω, 1 01 2.0 V/mV VOUT = ±2.5 V 2,3 1.0 VS = ±15 V, RL = 1.0 kΩ, 1 3.0 VOUT = ±10 V 2,3 1.5 See footnotes at end of table. STANDARD SIZE 5962-92117MICROCIRCUIT DRAWINGA DLA LAND AND MARITIME REVISION LEVEL SHEET COLUMBUS, OHIO 43218-3990 E 5 DSCC FORM 2234 APR 97 Document Outline DEPARTMENT OF DEFENSE SPECIFICATION DEPARTMENT OF DEFENSE STANDARDS
