Datasheet KSZ8765CLX (Microchip) - 9

KSZ8765CLX TABLE 2-1: SIGNALS - KSZ8765CLX (CONTINUED) Pin Pin Type Port Description Number Name Note 2-1
45 RXD5_0 Ipd/O 5 GMII/RGMII/MII/RMII: Port 5 Switch receive Bit[0]. 46 RXD5_1 Ipd/O 5 GMII/RGMII/MII/RMII: Port 5 Switch receive Bit[1]. 47 GNDD GND — Digital Ground. 48 VDDIO P — 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 49 RXD5_2 Ipd/O 5 GMII/RGMII/MII: Port 5 Switch receive Bit[2]. RMII: No connection 50 RXD5_3 Ipd/O 5 GMII/RGMII/MII: Port 5 Switch receive Bit[3]. RMII: No connection 51 RXDV5/ Ipd/O 5 GMII/MII: RXDV5 is for Port 5 switch GMII/MII receive data CRSDV5/ valid. RXD5_CTL RMII: CRSDV5 is for Port 5 RMII carrier sense/receive data valid output. RGMII: RXD5_CTL is for Port 5 RGMII receive data control 52 RXER5 Ipd/O 5 GMII/MII: Port 5 Switch receive error. RGMII/RMII: No connection. 53 CRS5 Ipd/O 5 GMII/MII: Port 5 Switch MII modes carrier sense. RGMII/RMII: No connection. 54 COL5 Ipd/O 5 GMII/MII: Port 5 Switch MII collision detect. RGMII/RMII: No connection. 55 REFCLKO Ipu/O — 25 MHz Clock Output (Option) Controlled by the strap pin LED2_0 and the Global Register 11 Bit[1]. Default is enabled; it is better to disable it if it’s not being used. 56 PME_N I/O — Power Management Event This output signal indicates that a WoL event has been detected as a result of a wake-up frame being detected. The KSZ8765- CLX is requesting the system to wake up from low power mode. Its assertion polarity is programmable with the default polarity to be active-low. 57 RXD5_4 Ipd/O 5 GMII: Port 5 switch receive Bit[4]. RGMII/MI/RMII: No connection. 58 RXD5_5 Ipd/O 5 GMII: Port 5 switch receive Bit[5]. RGMII/MII/RMII: No connection. 59 RXD5_6 Ipd/O 5 GMII: Port 5 switch receive Bit[6]. RGMII/MII/RMII: No connection. 60 RXD5_7 Ipd/O 5 GMII: Port 5 switch receive Bit[7]. RGMII/MII/RMII: No connection. 61 GNDD GND — Digital Ground.  2016 Microchip Technology Inc. DS00002130A-page 9 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines