KSZ8775CLX 1.0 INTRODUCTION 1.1 General Description The KSZ8775CLX is a highly integrated, Layer 2-managed, five-port switch with numerous features designed to reduce system cost. It is intended for cost-sensitive applications requiring three 10/100 Mbps copper ports, one RMII on Port 4, and one 10/100/1000Mbps Gigabit uplink port on Port 5. The KSZ8775CLX incorporates a small package outline, the lowest power consumption with internal biasing, and on-chip termination. Its extensive set of features include enhanced power management, programmable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet filtering technology, QoS priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8775CLX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the Port 5 GMAC can be configured to any of the RGMII, MII, and RMII modes. The KSZ8775CLX product is built upon industry-leading analog and digital technology, with features designed to offload host processing and streamline the overall design. • • • • Three integrated 10/100BASE-T/TX MAC/PHYs One integrated 10/100BASE-T/TX MAC with RMII interface One integrated 10/100/1000Base-T/TX GMAC with selectable RGMII, MII, and RMII interfaces Small 80-pin LQFP package A robust assortment of power management features including Energy Efficient Ethernet (EEE), power management event (PME), and Wake-on-LAN (WoL) have been designed in to satisfy energy efficient environments. All registers in the MAC/PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed through the MDC/MDIO interface. FIGURE 1-1: BLOCK DIAGRAM 2015 Microchip Technology Inc. DS00002129C-page 5
