KSZ8794CNX - QoS/CoS Packets Prioritization Support: tion in Transceivers in LPI State Even 802.1p, DiffServ-Based and Re-Mapping of Though Cables are Not Removed 802.1p Priority Field Per Port Basis on Four - Dynamic Clock Tree Control to Reduce Priority Levels Clocking in Areas that are Not in Use - IPv4/IPv6 QoS Support - Low Power Consumption without Extra - IPv6 Multicast Listener Discovery (MLD) Power Consumption on Transformers Snooping - Voltages: Using External LDO Power Sup- - Programmable Rate Limiting at the Ingress plies and Egress Ports on a Per Port Basis - Analog VDDAT 3.3V or 2.5V - Jitter-Free Per Packet Based Rate Limiting - VDDIO Support 3.3V, 2.5V, and 1.8V Support - Low 1.2V Voltage for Analog and Digital Core - Tail Tag Mode (1 byte Added before FCS) Power Support on Port 4 to Inform the Processor - WoL Support with Configurable Packet Con- which Ingress Port Receives the Packet trol - Broadcast Storm Protection with Percentage • Additional Features Control (Global and Per Port Basis) - Single 25 MHz ±50 ppm Reference Clock - 1K Entry Forwarding Table with 64 KB Frame Requirement Buffer - Comprehensive Programmable Two-LED - 4 Priority Queues with Dynamic Packet Map- Indicator Support for Link, Activity, Full-/Half- ping for IEEE 802.1P, IPv4 TOS (DIFF- Duplex, and 10/100 Speed SERV), IPv6 Traffic Class, etc. • Packaging and Environmental - Supports WoL Using AMD’s Magic Packet - Commercial Temperature Range: 0°C to - VLAN and Address Filtering +70°C - Supports 802.1x Port-Based Security, - Industrial Temperature Range: –40°C to Authentication and MAC-Based Authentica- +85°C tion via Access Control Lists (ACL) - Small Package Available in a Lead-Free, - Provides Port-Based and Rule-Based ACLs RoHS-Compliant 64-Pin QFN to Support Layer 2 MAC SA/DA Address, Layer 3 IP Address and IP Mask, Layer 4 - 0.065 µm CMOS Technology for Lower Power Consumption TCP/UDP Port Number, IP Protocol, TCP Flag and Compensation for the Port Security Filtering - Ingress and Egress Rate Limit Based on Bit per Second (bps) and Packet-Based Rate Limiting (pps) • Configuration Registers Access - High-Speed SPI (4-Wire, up to 50 MHz) Inter- face to Access All Internal Registers - MII Management (MIIM, MDC/MDIO 2-Wire) Interface to Access All PHY Registers per Clause 22.2.4.5 of the IEEE 802.3 Specifica- tion - I/O Pin Strapping Facility to Set Certain Reg- ister Bits from I/O Pins During Reset Time - Control Registers Configurable On-the-Fly • Power and Power Management - Full-Chip Software Power-Down (All Register Values are Not Saved and Strap-In Value Will Re-Strap After it Releases the Power-Down) - Per-Port Software Power-Down - Energy Detect Power-Down (EDPD), which Disables the PHY Transceiver When Cables are Removed - Supports IEEE P802.3az Energy Efficient Ethernet (EEE) to Reduce Power Consump- 2016 Microchip Technology Inc.
DS00002134A-page 2 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines
