Datasheet KSZ8863MLL, KSZ8863FLL, KSZ8863RLL (Microchip) - 7

KSZ8863MLL/FLL/RLL TABLE 2-1: SIGNALS (CONTINUED) Pin Pin Type Description Number Name Note 2-1
Switch MII/RMII receive data valid
Strap option:
Force duplex mode (P1DPX) PU = Port 1 default to full-duplex mode if P1ANEN = 1 and auto-negotia- 25 SMRXDV3 Ipu/O tion fails. Force port 1 in full-duplex mode if P1ANEN = 0. PD = Port 1 default to half-duplex mode if P1ANEN = 1 and auto-negotia- tion fails. Force port 1 in half-duplex mode if P1ANEN = 0. MLL/FLL: Switch MII receive data bit 3 RLL: Output reference clock in RMII mode. SMRXD33/ 26 Ipu/O REFCLKO_3
Strap option:
enable auto-negotiation on port 2 (P2ANEN) PU = Enable PD = Disable Switch MII receive data bit 2 27 SMRXD32 Ipu/O
Strap option:
Force the speed on port 2 (P2SPD) PU = Force port 2 to 100BT if P2ANEN = 0 PD = Force port 2 to 10BT if P2ANEN = 0 Switch MII/RMII receive data bit 1
Strap option:
Force duplex mode (P2DPX) PU = Port 2 default to full-duplex mode if P2ANEN = 1 and auto-negotia- 28 SMRXD31 Ipu/O tion fails. Force port 2 in full-duplex mode if P2ANEN = 0. PD = Port 2 set to half-duplex mode if P2ANEN = 1 and auto-negotiation fails. Force port 2 in half-duplex mode if P2ANEN = 0. Switch MII/RMII receive data bit 0
Strap option:
Force flow control on port 2 (P2FFC) 29 SMRXD30 Ipu/O PU = Always enable (force) port 2 flow control feature. PD = Port 2 flow control feature enable is determined by auto-negotiation result. Switch MII receive clock. 30 SMRXC3 I/O Output in PHY MII mode Input in MAC MII mode 31 GND GND Digital ground 32 VDDC P 1.8V digital core power input from VDDCO (pin 42) 33 SCOL3 Ipu/O Switch MII collision detect 34 SCRS3 Ipu/O Switch MII carrier sense Interrupt 35 INTRN Opu Active-low signal to host CPU to indicate an interrupt status bit is set when lost link. Refer to register 187 and 188. SPI Slave mode/I2C Slave mode: clock input 36 SCL_MDC I/O I2C Master mode: clock output MIIM clock input SPI Slave mode: serial data input I2C Master/Slave mode: serial data input/output 37 SDA_MDIO Ipu/O MIIM: Data input/output Note: An external pull-up is needed on this pin when it is in use. SPI Slave mode: serial data output Note: An external pull-up is needed on this pin when it is in use. 38 SPIQ Ipd/O
Strap option:
Force flow control on port 1 (P1FFC) PU = Always enable (force) port 1 flow control feature PD = Port 1 flow control feature enable is determined by auto-negotiation result.  2017 Microchip Technology Inc. DS00002335B-page 7 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Timing 7.7 Auto-Negotiation Timing 7.8 MDC/MDIO Timing 7.9 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service