Datasheet KSZ8873MLL, KSZ8873FLL, KSZ8873RLL (Microchip) - 3

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KSZ8873MLL/FLL/RLL Table of Contents
1.0 Introduction ... 4 2.0 Pin Description and Configuration .. 5 3.0 Functional Description .. 12 4.0 Register Descriptions .. 38 5.0 Operational Characteristics ... 74 6.0 Electrical Characteristics ... 75 7.0 Timing Specifications .. 77 8.0 Reset Circuit ... 88 9.0 Selection of Isolation Transformers .. 89 10.0 Package Outline .. 90 Appendix A: Data Sheet Revision History ... 91 The Microchip Web Site .. 92 Customer Change Notification Service ... 92 Customer Support ... 92 Product Identification System ... 93  2017 Microchip Technology Inc. DS00002348A-page 3 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Input Timing 7.7 SPI Output Timing 7.8 Auto-Negotiation Timing 7.9 MDC/MDIO Timing 7.10 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service