Micrel, Inc. KS8995XA Reset Circuit Diagram Micrel recommends the following discrete reset circuit as shown in Figure 16 when powering up the KS8895XA device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), we recommend the reset circuit as shown in Figure 17. VCC D1: 1N4148 KS8995XA R 10k D1 RST C 10µF Figure 16. Recommended Reset Circuit VCC KS8995XA R 10k D1 CPU/FPGA RST RST_OUT_n D2 C 10µF D1, D2: 1N4148 Figure 17. Recommended Circuit for Interfacing with CPU/FPGA Reset At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time. September 2008 53 M9999-091508
