LAN93521.0PREFACE1.1General TermsTABLE 1-1:GENERAL TERMSTermDescription10BASE-T 10 Mbps Ethernet, IEEE 802.3 compliant 100BASE-TX 100 Mbps Fast Ethernet, IEEE802.3u compliant ADC Analog-to-Digital Converter ALR Address Logic Resolution AN Auto-Negotiation BLW Baseline Wander BM Buffer Manager - Part of the switch fabric BPDU Bridge Protocol Data Unit - Messages which carry the Spanning Tree Protocol informa- tion Byte 8 bits CSMA/CD Carrier Sense Multiple Access/Collision Detect CSR Control and Status Registers CTR Counter DA Destination Address DWORD 32 bits EPC EEPROM Controller FCS Frame Check Sequence - The extra checksum characters added to the end of an Ethernet frame, used for error detection and correction. FIFO First In First Out buffer FSM Finite State Machine GPIO General Purpose I/O Host External system (Includes processor, application software, etc.) IGMP Internet Group Management Protocol Inbound Refers to data input to the device
from the host Level-Triggered Sticky Bit This type of status bit is set whenever the condition that it represents is asserted. The bit remains set until the condition is no longer true and the status bit is cleared by writ- ing a zero. lsb Least Significant Bit LSB Least Significant Byte LVDS Low Voltage Differential Signaling MDI Medium Dependent Interface MDIX Media Independent Interface with Crossover MII Media Independent Interface MIIM Media Independent Interface Management MIL MAC Interface Layer MLD Multicast Listening Discovery MLT-3 Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”. msb Most Significant Bit MSB Most Significant Byte DS00001923A-page 4 2015 Microchip Technology Inc. Document Outline Highlights Target Applications Key Benefits 1.0 Preface TABLE 1-1: General Terms TABLE 1-2: Buffer Types TABLE 1-3: Register Nomenclature 2.0 General Description FIGURE 2-1: Internal Block Diagram 3.0 Pin Descriptions and Configuration FIGURE 3-1: 72-QFN Pin Assignments (Top View) TABLE 3-1: 72-QFN Package Pin Assignments FIGURE 3-2: 80-TQFP-EP Pin Assignments (Top View) TABLE 3-2: 80-TQFP-EP Package Pin Assignments TABLE 3-3: LAN Port A Pin Descriptions TABLE 3-4: LAN Port B Pin Descriptions TABLE 3-5: LAN Port A & B Power and Common Pin Descriptions TABLE 3-6: Host Bus Pin Descriptions TABLE 3-7: SPI/SQI Pin Descriptions TABLE 3-8: EEPROM Pin Descriptions TABLE 3-9: GPIO, LED & Configuration Strap Pin Descriptions TABLE 3-10: Miscellaneous Pin Descriptions TABLE 3-11: JTAG Pin Descriptions TABLE 3-12: Core and I/O Power Pin Descriptions 4.0 Power Connections FIGURE 4-1: Power Connections - Regulators Enabled FIGURE 4-2: Power Connections - Regulators Disabled 5.0 Register Map FIGURE 5-1: Register Address Map TABLE 5-1: System Control and Status Registers TABLE 5-2: Read After Write Timing Rules TABLE 5-3: Read After Read Timing Rules 6.0 Clocks, Resets, and Power Management TABLE 6-1: Reset Sources and Affected Device Functionality FIGURE 6-1: PME Pin and PME Interrupt Signal Generation TABLE 6-2: Power Management States 7.0 Configuration Straps TABLE 7-1: Soft-Strap Configuration Strap Definitions TABLE 7-2: Hard-Strap Configuration Strap Definitions TABLE 7-3: HBI Strap Mapping 8.0 System Interrupts FIGURE 8-1: Functional Interrupt Hierarchy TABLE 8-1: Interrupt Registers 9.0 Host Bus Interface FIGURE 9-1: Little Endian Ordering FIGURE 9-2: Big Endian Ordering FIGURE 9-3: Multiplexed Addressing with Dual Phase Latching - 16-Bit Read FIGURE 9-4: Multiplexed Addressing with Dual Phase Latching - 16-Bit Read Without ALEHI FIGURE 9-5: Multiplexed Addressing with Dual Phase Latching - 16-Bit Write FIGURE 9-6: Multiplexed Addressing with Dual Phase Latching - 16-Bit Write Without ALEHI FIGURE 9-7: Multiplexed Addressing with Dual Phase Latching - 16-Bit Reads and Writes Constant Address FIGURE 9-8: Multiplexed Addressing with Dual Phase Latching - 8-Bit Reads FIGURE 9-9: Multiplexed Addressing with Dual Phase Latching - 8-Bit Reads Without ALEHI FIGURE 9-10: Multiplexed Addressing with Dual Phase Latching - 8-Bit Write FIGURE 9-11: Multiplexed Addressing with Dual Phase Latching - 8-Bit Write Without ALEHI FIGURE 9-12: Multiplexed Addressing with Dual Phase Latching - 8-Bit Reads and Writes Constant Address FIGURE 9-13: Multiplexed Addressing with Single Phase Latching - 16-Bit Read FIGURE 9-14: Multiplexed Addressing with Single Phase Latching - 16-Bit Write FIGURE 9-15: Multiplexed Addressing with Single Phase Latching - 16-Bit Reads and Writes Constant Address FIGURE 9-16: Multiplexed Addressing with Single Phase Latching - 8-Bit Read FIGURE 9-17: Multiplexed Addressing with Single Phase Latching - 8-Bit Write FIGURE 9-18: Multiplexed Addressing with Single Phase Latching - 8-Bit Reads and Writes Constant Address FIGURE 9-19: Multiplexed Addressing RD_WR / ENB Control Mode Example - 16- Bit Read FIGURE 9-20: Multiplexed Addressing RD_WR / ENB Control Mode Example - 16- Bit Write FIGURE 9-21: Multiplexed Addressing Read Cycle Timing TABLE 9-1: Multiplexed Addressing Read Cycle Timing Values FIGURE 9-22: Multiplexed Addressing Write Cycle Timing TABLE 9-2: Multiplexed Addressing Write Cycle Timing Values TABLE 9-3: Host Bus Interface Indexed Address Mode Register Map FIGURE 9-23: Little Endian Ordering FIGURE 9-24: Big Endian Ordering FIGURE 9-25: Indexed Addressing Configuration Register Access - 16-Bit Write/ Read FIGURE 9-26: Indexed Addressing Configuration Register Access - 8-Bit Write/ Read FIGURE 9-27: Indexed Addressing Index Register Access - 16-Bit Write/Read FIGURE 9-28: Indexed Addressing Index Register Access - 8-Bit Write/Read FIGURE 9-29: Indexed Addressing Internal Register Data Access - 16-Bit Read FIGURE 9-30: Indexed Addressing Internal Register Data Access - 16-Bit Write FIGURE 9-31: Indexed Addressing Internal Register Data Access - 16-Bit Reads/ Writes Constant Address FIGURE 9-32: Indexed Addressing Internal Register Data Access - 8-Bit Read FIGURE 9-33: Indexed Addressing Internal Register Data Access - 8-Bit Write FIGURE 9-34: Indexed Addressing Internal Register Data Access - 8-Bit Reads/ Writes Constant Address FIGURE 9-35: Indexed Addressing FIFO Direct Select Access - 16-Bit Read FIGURE 9-36: Indexed Addressing FIFO Direct Select Access - 16-Bit Write FIGURE 9-37: Indexed Addressing FIFO Direct Select Access - 16-Bit Burst Read FIGURE 9-38: Indexed Addressing FIFO Direct Select Access - 8-Bit Read FIGURE 9-39: Indexed Addressing FIFO Direct Select Access - 8-Bit Write FIGURE 9-40: Indexed Addressing FIFO Direct Select Access - 8-Bit Burst Read FIGURE 9-41: Indexed Addressing RD_WR / ENB Control Mode Example - 16-Bit Write/Read FIGURE 9-42: Indexed Addressing Read Cycle Timing TABLE 9-4: Indexed Addressing Read Cycle Timing Values FIGURE 9-43: Indexed Addressing FIFO Direct Select Burst Read Cycle Timing TABLE 9-5: Indexed Addressing FIFO Direct Select Burst Read Cycle Timing Values FIGURE 9-44: Indexed Addressing Write Cycle Timing TABLE 9-6: Indexed Addressing Write Cycle Timing Values 10.0 SPI/SQI Slave TABLE 10-1: SPI Instructions TABLE 10-2: SQI Instructions FIGURE 10-1: Enable SQI FIGURE 10-2: SPI Mode Reset SQI FIGURE 10-3: SQI Mode Reset SQI FIGURE 10-4: SPI Read FIGURE 10-5: SPI Fast Read FIGURE 10-6: SQI Fast Read FIGURE 10-7: SPI Dual Output Read FIGURE 10-8: SPI Quad Output Read FIGURE 10-9: SPI Dual I/O Read FIGURE 10-10: SPI Quad I/O Read FIGURE 10-11: SPI Write FIGURE 10-12: SQI Write FIGURE 10-13: SPI Dual Data Write FIGURE 10-14: SPI Quad Data Write FIGURE 10-15: SPI Dual Address / Data Write FIGURE 10-16: SPI Quad Address / Data Write FIGURE 10-17: SPI/SQI Input Timing FIGURE 10-18: SPI/SQI Output Timing TABLE 10-3: SPI/SQI Timing Values 11.0 Host MAC FIGURE 11-1: VLAN Frame TABLE 11-1: Address Filtering Modes TABLE 11-2: Wakeup Frame Filter Register Structure TABLE 11-3: Filter i Byte Mask Bit Definitions TABLE 11-4: Filter i Command Bit Definitions TABLE 11-5: Filter i Offset Bit Definitions TABLE 11-6: Filter i CRC-16 Bit Definitions TABLE 11-7: Wakeup Generation Cases FIGURE 11-2: RXCOE Checksum Calculation FIGURE 11-3: Type II Ethernet Frames FIGURE 11-4: Ethernet Frame With VLAN Tag FIGURE 11-5: Ethernet Frame With Length Field and SNAP Header FIGURE 11-6: Ethernet Frame With VLAN Tag and SNAP Header FIGURE 11-7: Ethernet Frame With Multiple VLAN Tags and SNAP Header TABLE 11-8: TX Checksum Preamble FIGURE 11-8: TX Example Illustrating a Prepended TX Checksum Preamble TABLE 11-9: EEPROM Byte Ordering and Register Correlation FIGURE 11-9: Example EEPROM MAC Address Setup TABLE 11-10: TX/RX FIFO Configurable Sizes TABLE 11-11: Valid TX/RX FIFO Allocations FIGURE 11-10: Simplified Host TX Flow Diagram FIGURE 11-11: TX Buffer Format TABLE 11-12: TX Command 'A' Format TABLE 11-13: TX Command 'B' Format TABLE 11-14: TX DATA Start Offset FIGURE 11-12: TX Example 1 FIGURE 11-13: TX Example 2 FIGURE 11-14: TX Example 3 FIGURE 11-15: Host Receive Routine Using Interrupts FIGURE 11-16: Host Receive Routine Using Polling FIGURE 11-17: RX Packet Format TABLE 11-15: Host MAC & FIFO Interface Logic Registers TABLE 11-16: Backpressure Duration Bit Mapping TABLE 11-17: Host MAC Addressable Registers 12.0 Ethernet PHYs TABLE 12-1: Default PHY Serial MII Addressing FIGURE 12-1: Physical PHY Block Diagram FIGURE 12-2: 100BASE-TX Transmit Data Path TABLE 12-2: 4B/5B Code Table FIGURE 12-3: 100BASE-TX Receive Data Path FIGURE 12-4: Direct Cable Connection vs. Cross-Over Cable Connection TABLE 12-3: Interrupt Management Table TABLE 12-4: Alternative Interrupt Mode Management Table TABLE 12-5: Wakeup Generation Cases FIGURE 12-5: TDR Usage Flow Diagram TABLE 12-6: TDR Propagation Constants TABLE 12-7: Typical Measurement Error for Open Cable (+/- Meters) TABLE 12-8: Typical Measurement Error for Shorted Cable (+/- Meters) TABLE 12-9: Match Case Estimated Cable Length (CBLN) Lookup FIGURE 12-6: Near-end Loopback Block Diagram FIGURE 12-7: Connection Loopback Block Diagram TABLE 12-10: 100BASE-FX LOS, SD and TP Copper Selection PHY A TABLE 12-11: 100BASE-FX LOS, SD and TP Copper Selection PHY B TABLE 12-12: Physical PHY A and B MII Serially Accessible Control and Status Registers TABLE 12-13: 10BASE-T Full Duplex Advertisement Default Value TABLE 12-14: 10BASE-T Half Duplex Advertisement Bit Default Value TABLE 12-15: MODE[2:0] Definitions TABLE 12-16: Auto-MDIX Enable and Auto-MDIX State Bit Functionality TABLE 12-17: MDIX Strap Functionality TABLE 12-18: MMD Registers TABLE 12-19: Virtual PHY MII Serially Addressable Register Index TABLE 12-20: Emulated Link Partner Pause Flow Control Ability Default Values 13.0 Switch Fabric FIGURE 13-1: ALR Table Entry Structure FIGURE 13-2: Switch Engine Transmit Queue Selection FIGURE 13-3: Switch Engine Transmit Queue Calculation FIGURE 13-4: VLAN Table Entry Structure TABLE 13-1: Spanning Tree States TABLE 13-2: Typical Ingress Rate Settings FIGURE 13-5: Switch Engine Ingress Flow Priority Selection FIGURE 13-6: Switch Engine Ingress Flow Priority Calculation TABLE 13-3: Typical Broadcast Rate Settings TABLE 13-4: Typical Egress Rate Settings FIGURE 13-7: Hybrid Port Tagging and Un-Tagging TABLE 13-5: Switch Fabric Flow Control Enable Logic FIGURE 13-8: Switch Fabrics CSR Write Access Flow Diagram FIGURE 13-9: Switch Fabrics CSR Read Access Flow Diagram TABLE 13-6: Switch Fabric Interface Logic Registers TABLE 13-7: SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH and EEPROM Byte Ordering FIGURE 13-10: Example SWITCH_MAC_ADDL, SWITCH_MAC_ADDRH and EEPROM Setup TABLE 13-8: Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map TABLE 13-9: Indirectly Accessible Switch Control and Status Registers TABLE 13-10: Metering/Color Table Register Descriptions 14.0 I2C Master EEPROM Controller FIGURE 14-1: I2C Cycle FIGURE 14-2: I2C Master Timing TABLE 14-1: I2C Master Timing Values TABLE 14-2: I2C EEPROM Size Ranges FIGURE 14-3: I2C EEPROM Addressing FIGURE 14-4: I2C EEPROM Byte Read FIGURE 14-5: I2C EEPROM Sequential Byte Reads FIGURE 14-6: I2C EEPROM Byte Write FIGURE 14-7: EEPROM Access Flow Diagram TABLE 14-3: EEPROM Contents Format Overview FIGURE 14-8: EEPROM Loader Flow Diagram TABLE 14-4: EEPROM Configuration Bits TABLE 14-5: I2C Master EEPROM Controller Registers 15.0 IEEE 1588 FIGURE 15-1: 1588 Clock Block Diagram FIGURE 15-2: 1588 Clock Event Block Diagram TABLE 15-1: 1588 Control and Status Registers 16.0 General Purpose Timer & Free-Running Clock TABLE 16-1: Miscellaneous Registers 17.0 GPIO/LED Controller TABLE 17-1: LED Operation as a Function of LED_FUN[2:0] = 000b - 011b TABLE 17-2: LED Operation as a Function of LED_FUN[2:0] = 100b - 111b TABLE 17-3: GPIO/LED Registers 18.0 Miscellaneous TABLE 18-1: Miscellaneous Registers 19.0 JTAG TABLE 19-1: IEEE 1149.1 Op Codes FIGURE 19-1: JTAG Timing TABLE 19-2: JTAG Timing Values 20.0 Operational Characteristics TABLE 20-1: 72-PIN QFN Package Thermal Parameters TABLE 20-2: 80-PIN TQFP-EP Package Thermal Parameters TABLE 20-3: Maximum Power Dissipation TABLE 20-4: Current Consumption and Power Dissipation (Regs. Disabled) TABLE 20-5: Current Consumption and Power Dissipation (Regs. Enabled) TABLE 20-6: Non-Variable I/O DC Electrical Characteristics TABLE 20-7: Variable I/O DC Electrical Characteristics TABLE 20-8: 100BASE-TX Transceiver Characteristics TABLE 20-9: 10BASE-T Transceiver Characteristics FIGURE 20-1: Output Equivalent Test Load FIGURE 20-2: Power Sequence Timing - Internal Regulators FIGURE 20-3: Power Sequence Timing - External Regulators TABLE 20-10: Power Sequencing Timing Values FIGURE 20-4: RST# Pin Configuration Strap Latching Timing TABLE 20-11: RST# Pin Configuration Strap Latching Timing Values FIGURE 20-5: Power-On Configuration Strap Latching Timing TABLE 20-12: Power-On Configuration Strap Latching Timing Values TABLE 20-13: Crystal Specifications 21.0 Package Outlines FIGURE 21-1: 72-QFN Package FIGURE 21-2: 72-QFN Package Dimensions FIGURE 21-3: 80-TQFP-EP Package 22.0 Revision History TABLE 22-1: Revision History The Microchip Web Site Product Identification System Worldwide Sales and Service
