Datasheet LTC2500-32 (Analog Devices) - 6

LTC2500-32
DIGITAL INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l 0.8 • 0VDD V VIL Low Level Input Voltage l 0.2 • OVDD V IIN Digital Input Current VIN = 0V to OVDD l –10 10 µA CIN Digital Input Capacitance 5 pF VOH High Level Output Voltage IO = –500 µA l OVDD – 0.2 V VOL Low Level Output Voltage IO = 500 µA l 0.2 V IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l –10 10 µA ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = OVDD 10 mA
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l 2.375 2.5 2.625 V OVDD Supply Voltage l 1.71 5.25 V IVDD Supply Current 1Msps Sample Rate l 9.5 14 mA IOVDD Supply Current 1Msps Sample Rate (CL = 20pF) 1 mA IPD Power Down Mode Conversion Done (IVDD + IOVDD + IREF) l 6 350 µA PD Power Dissipation 1Msps Sample Rate (IVDD) 24 35 mW Power Down Mode Conversion Done (IVDD + IOVDD + IREF) 15 875 µW
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l 1 Msps fDRA Output Data Rate at SDOA l 250 ksps fDRB Output Data Rate at SDOB l 1 Msps tCONV Conversion Time l 600 660 ns tACQ Acquisition Time tACQ = tCYC – tCONV – tBUSYLH (Note 12) l 327 ns tCYC Time Between Conversions l 1000 ns tMCLKH Conversion High Time l 20 ns tMCLKL Minimum Low Time for MCLK (Note 13) l 20 ns tBUSYLH MCLK to BUSY Delay CL = 20pF l 13 ns tQUIET SCKA, SCKB Quiet Time from MCLK (Note 12) l 10 ns tSCKA SCKA Period (Notes 13, 14) l 10 ns tSCKAH SCKA High Time l 4 ns tSCKAL SCKA Low Time l 4 ns tSSDISCKA SD1 Setup Time from SCKA (Note 13) l 4 ns tHSDISCKA SD1 Hold Time from SCKA (Note 13) l 1 ns tDSDOA SDOA Data Valid Delay from SCKA CL = 20pF, OVDD = 5.25V l 8.5 ns CL = 20pF, OVDD = 2.5V l 8.5 ns CL = 20pF, OVDD = 1.71V l 9.5 ns 250032fb 6 For more information www.linear.com/LTC2500-32 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Converter Characteristics for Filtered Output (SDOA) Dynamic Accuracy for Filtered Output (SDOA) Converter Characteristics for No latency Output (SDOB) Dynamic Accuracy for No Latency Output (SDOB) Reference Input Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Overview Converter Operation Transfer Function Analog Input Input Drive Circuits ADC Reference Dynamic Performance Power Considerations Timing and Control Decimation Filters Digital Filter Types Digital Interface Preset Filter Modes Filtered Output Data No Latency Output Data Board Layout Package Description Revision History Typical Application Related Parts