LT3964 PIN FUNCTIONSRT (Pin 1): Switching Frequency Adjustment Pin. Set the ALERT (Pin 6): Chip Alert Status Report Pin. An open- master clock frequency using a resistor to GND (for resis- collector pull-down on ALERT asserts when any of the tor values, see Typical Performance curve or Table 3). Do following conditions happen: not leave the RT pin open. 1. FB Overvoltage (VFB > 1.233V); CTRL1, CTRL2 (Pins 2, 3): Current Sense Threshold 2. OPENLED (V Adjustment Pins. The V FB > 1.127V and V(ISP-ISN) <10mV); (ISP-ISN) threshold is regulated by the internal 1.2V reference voltage, CTRL and ADIM[7:0] 3. SHORTLED (VFB < 0.25V); of the respective channel as follows: 4. LED Overcurrent (V(ISP-ISN) > 930mV); V(ISP-ISN) = 0V, when VCTRL < 0.2V 5. INTVCC undervoltage; or V(ISP-ISN) = [(VCTRL –0.2V)/10]•(ADIM[7:0]+1)/256, 6. Thermal shutdown. when 0.2V ≤ VCTRL ≤ 1.1V ALERT flag stays low until all alerts have been removed V(ISP-ISN) = 100mV•(ADIM[7:0]+1)/256, when VCTRL > 1.3V and unlatched. For 1.1V < VCTRL < 1.3V, the dependence of the current PWM1, PWM2 (Pins 7, 8): PWM Input Signal Pin. A sense threshold upon VCTRL transitions from a linear low signal turns off switching, reduces quiescent supply function to a constant value, reaching 98% of full scale current, and drives PWMTG to the ISP level. PWM has value, 100mV•(ADIM[7:0]+1)/256, by VCTRL = 1.2V. See an internal 280k pull-down resistor. If not used, connect Table 1 for detailed information. Do not leave this pin open. this pin to INTVCC. EN/UVLO (Pin 4): Enable and Undervoltage Lockout Pin. SDA (Pin 9): Serial Data Line for I2C Port. Open-drain An accurate 1.18V falling threshold with externally pro- output during read back. grammable hysteresis detects when power is OK to enable switching. Rising hysteresis is generated by the external SCL (Pin 10): Serial Clock Line for I2C Port. resistor divider and an accurate internal 4µA pull-down ADDR2 (Pin 11): Address Select Pin. This pin is configured current. Tie to 0.4V or less to disable the device. as a three-state (LOW, HIGH, FLOAT) address control bit for INTV the device I2C address. See Table 14 for address selection. CC (Pin 5): Internal Low-Dropout Regulator Output. INTVCC is regulated to 4V, and must be bypassed with an ADDR1 (Pin 12): Address Select Pin. This pin is configured external capacitor of at least 2.2μF. INTVCC is the power as a three-state (LOW, HIGH, FLOAT) address control bit for supply for the internal DMOS gate driver and control the device I2C address. See Table 14 for address selection. circuitry. Users may apply <5mA loads to INTVCC. Over- loading INTV VIN2 (Pins 13, 14): Input Supply for Channel 2. May be CC can cause unintentional device shutdown from INTV driven by an independent supply, or connected to VIN1. CC current limiting or overheating due to power dissipation. This signal must be locally bypassed. Be sure to place the positive terminal of the input capacitor as close as pos- sible to the VIN2 pin, and the negative terminal as close as possible to the PGND pin (Pin 37). 3964fb 10 For more information www.linear.com/LT3964
