Datasheet AD5750, AD5750-1, AD5750-2 (Analog Devices) - 9

Data Sheet AD5750/AD5750-1/AD5750-2 Timing Diagrams t1 SCLK 1 2 16 t t 3 2 t6 t t 4 5 SYNC t8 t7 SDIN D15 D0 CLEAR t10 t9 VOUT RESET t
003
13
07268- Figure 2. Write Mode Timing Diagram
SCLK t SYNC 11 A2 SDIN A1 A0 R = 1 0 R3 R2 R1 R0 CLRSEL OUTEN CLEAR RSET RESET 0 0 t12 SDO X X X X X R3 R2 R1 R0 PEC OVER IOUT VOUT CLRSEL OUTEN RSET
004
ERROR TEMP FAULT FAULT
07268- Figure 3. Readback Mode Timing Diagram Rev. F | Page 9 of 36 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications Timing Characteristics Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Voltage Output Current Output Terminology Theory of Operation Software Mode Current Output Architecture Driving Inductive Loads Voltage Output Amplifier Driving Large Capacitive Loads Power-On State of AD5750/AD5750-1/AD5750-2 Default Registers at Power-On Reset Function OUTEN Software Control Input Shift Register Status Bit Read Operation Hardware Control Transfer Function Detailed Description of Features Output Fault Alert—Software Mode Output Fault Alert—Hardware Mode Voltage Output Short-Circuit Protection Asynchronous Clear (CLEAR) External Current Setting Resistor Programmable Overrange Modes Packet Error Checking Applications Information Transient Voltage Protection Thermal Considerations Layout Guidelines Galvanically Isolated Interface Microprocessor Interfacing Outline Dimensions Ordering Guide