Datasheet AD8341 (Analog Devices) - 18

AD8341 Data Sheet Components Function Default Conditions
C2, C4, C7, Supply Decoupling. C2, C4, C7, C9, C14 = 0.1 μF C9, C14, C1, (Size 0603) C3, C8, C10, C1, C3, C8, C10 = 100 pF R2, R4, R5, R6 (Size 0603) R2, R4, R5, R6 = 0 Ω (Size 0603) R8, SW1 Output Disable Interface. The output stage of the AD8341 is disabled by applying a high R8 = 10 kΩ (Size 0603) voltage to the DSOP pin by moving SW1 to Position B. The output stage is enabled moving SW1 = SPDT (Position A, SW1 to Position A. The output disable function can also be exercised by applying an Output Enabled) external high or low voltage to the DSOP SMA connector with SW1 in Position A.
IBBP IBBM R9 C19 R7 0.1
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F VP GND (OPEN) (OPEN) TEST POINT TEST POINT R19 0 W4 W3 C2 R21 C15 R20 0.1
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F 0 0.1
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F 0 R2 VS 0 R14 R11 R15 4k 2k 44k C1 100pF C12 (OPEN) B SW1 R8 A C7 C8 R5 10k DSOP 0.1
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F 100pF IFLP DSOP 0 VS VPRF IFLM IBBP IBBM VPS2 CMOP T1 C6 L3 CMRF CMOP C18 ETC1-1-13 100pF 1.2nH 100pF M/A-COM RFIN RFOM AD8341 RFIN RFIP RFOP RFOP L4 C5 C17 1.2nH 100pF L2 L1 CMRF CMOP 100pF 120nH 120nH VP VPRF CMOP R4 C4 C3 QFLP QFLM QBBP QBBM VPS2 VPS2 C14 0 0.1
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F 100pF 0.1
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F VP C11 C10 R6 C9 (OPEN) 100pF 0 0.1
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F R12 R10 R13 4k 2k 44k VS C16 0.1
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F W2 W1 R17 R18 0 R16 0 0 R1 R3 (OPEN) C20 (OPEN) 0.1
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F QBBP QBBM
04700-041 Figure 41. Evaluation Board Schematic Rev. B | Page 18 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RF QUADRATURE GENERATOR I-Q ATTENUATORS AND BASEBAND AMPLIFIERS OUTPUT AMPLIFIER NOISE AND DISTORTION GAIN AND PHASE ACCURACY RF FREQUENCY RANGE APPLICATIONS INFORMATION USING THE AD8341 RF INPUT AND MATCHING RF OUTPUT AND MATCHING DRIVING THE I-Q BASEBAND CONTROLS INTERFACING TO HIGH SPEED DACs CDMA2000 APPLICATION WCDMA APPLICATION EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE