LT8315 BLOCK DIAGRAM DOUT NPS:1 VIN V + OUT CIN ZSNUB • L C PRI LSEC OUT DSNUB • V – OUT DRAIN BIAS 9 630V 1, 2, 3 LDO DEPLETION CBIAS – 10V VUVLO + FET M2 DBIAS + – INTVCC 8 EN/UVLO MASTER 630V 17 LATCH BIAS/REF POWER CINTVCC CONTROL S FET SMODE TSD 16 Q DRIVER M1 R CDCM RDCM DCM SOURCE 10 BOUNDARY 18 DETECT CURRENT VOLTAGE COMPARATOR CONTROLLED RSNS OSCILLATOR + ×10 GND :NTS RFB2 • 15, 20, 21 FB 12 ×1 S&H L – TER RFB1 RTC TC 11 ×1 VOLTAGE CURRENT 1.25×(1–D) ERROR AMP ERROR AMP +4.1mV/°C – GM – 1.22V + 10µA + VC IREG/SS 13 14 8315 BD RC RIREG CC 8315fa 8 For more information www.linear.com/LT8315 Document Outline FEATURES APPLICATIONS DESCRIPTION TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM OPERATION APPLICATIONS INFORMATION PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
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