Datasheet Complete ATmega48/V, ATmega88/V, ATmega168/V (Atmel) - 3

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Table of Contents
Introduction..1 Feature.. 1 1. Description...10 2. Configuration Summary... 11 3. Ordering Information ...12 3.1. ATmega48/V...12 3.2. ATmega88/V...13 3.3. ATmega168/V...14 4. Block Diagram... 15 5. Pin Configurations... 16 5.1. Pin-out.. 16 5.2. Pin Descriptions..19 6. I/O Multiplexing.. 21 7. Resources..23 8. Data Retention...24 9. About Code Examples... 25 10. Capacitive Touch Sensing... 26 10.1. QTouch Library... 26 11. AVR CPU Core.. 27 11.1. Overview...27 11.2. ALU – Arithmetic Logic Unit..28 11.3. Status Register...28 11.4. General Purpose Register File... 30 11.5. Stack Pointer.. 31 11.6. Instruction Execution Timing.. 33 11.7. Reset and Interrupt Handling... 34 12. AVR Memories...36 12.1. Overview...36 12.2. In-System Reprogrammable Flash Program Memory..36 12.3. SRAM Data Memory...37 12.4. EEPROM Data Memory... 39 12.5. I/O Memory...40 12.6. Register Description... 41 Document Outline Introduction Feature Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 3.1. ATmega48/V 3.2. ATmega88/V 3.3. ATmega168/V 4. Block Diagram 5. Pin Configurations 5.1. Pin-out 5.2. Pin Descriptions 5.2.1. VCC 5.2.2. GND 5.2.3. Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2 5.2.4. Port C (PC[5:0]) 5.2.5. PC6/RESET 5.2.6. Port D (PD[7:0]) 5.2.7. AVCC 5.2.8. AREF 5.2.9. ADC[7:6] (TQFP and VFQFN Package Only) 6. I/O Multiplexing 7. Resources 8. Data Retention 9. About Code Examples 10. Capacitive Touch Sensing 10.1. QTouch Library 11. AVR CPU Core 11.1. Overview 11.2. ALU – Arithmetic Logic Unit 11.3. Status Register 11.3.1. Status Register 11.4. General Purpose Register File 11.4.1. The X-register, Y-register, and Z-register 11.5. Stack Pointer 11.5.1. Stack Pointer Register High byte 11.5.2. Stack Pointer Register Low byte 11.6. Instruction Execution Timing 11.7. Reset and Interrupt Handling 11.7.1. Interrupt Response Time 12. AVR Memories 12.1. Overview 12.2. In-System Reprogrammable Flash Program Memory 12.3. SRAM Data Memory 12.3.1. Data Memory Access Times 12.4. EEPROM Data Memory 12.4.1. EEPROM Read/Write Access 12.4.2. Preventing EEPROM Corruption 12.5. I/O Memory 12.5.1. General Purpose I/O Registers 12.6. Register Description 12.6.1. EEPROM Address Register High 12.6.2. EEPROM Address Register Low 12.6.3. EEPROM Data Register 12.6.4. EEPROM Control Register 12.6.5. GPIOR2 – General Purpose I/O Register 2 12.6.6. GPIOR1 – General Purpose I/O Register 1 12.6.7. GPIOR0 – General Purpose I/O Register 0 13. System Clock and Clock Options 13.1. Clock Systems and Their Distribution 13.1.1. CPU Clock – clkCPU 13.1.2. I/O Clock – clkI/O 13.1.3. Flash Clock – clkFLASH 13.1.4. Asynchronous Timer Clock – clkASY 13.1.5. ADC Clock – clkADC 13.2. Clock Sources 13.2.1. Default Clock Source 13.2.2. Clock Startup Sequence 13.2.3. Clock Source Connections 13.3. Low Power Crystal Oscillator 13.4. Full Swing Crystal Oscillator 13.5. Low Frequency Crystal Oscillator 13.6. Calibrated Internal RC Oscillator 13.7. 128kHz Internal Oscillator 13.8. External Clock 13.9. Timer/Counter Oscillator 13.10. Clock Output Buffer 13.11. System Clock Prescaler 13.12. Register Description 13.12.1. Oscillator Calibration Register 13.12.2. Clock Prescaler Register 14. PM - Power Management and Sleep Modes 14.1. Overview 14.2. Sleep Modes 14.3. Idle Mode 14.4. ADC Noise Reduction Mode 14.5. Power-Down Mode 14.6. Power-save Mode 14.7. Standby Mode 14.8. Extended Standby Mode 14.9. Power Reduction Register 14.10. Minimizing Power Consumption 14.10.1. Analog to Digital Converter 14.10.2. Analog Comparator 14.10.3. Brown-Out Detector 14.10.4. Internal Voltage Reference 14.10.5. Watchdog Timer 14.10.6. Port Pins 14.10.7. On-chip Debug System 14.11. Register Description 14.11.1. Sleep Mode Control Register 14.11.2. MCU Control Register 14.11.3. Power Reduction Register 15. SCRST - System Control and Reset 15.1. Resetting the AVR 15.2. Reset Sources 15.3. Power-on Reset 15.4. External Reset 15.5. Brown-out Detection 15.6. Watchdog System Reset 15.7. Internal Voltage Reference 15.7.1. Voltage Reference Enable Signals and Start-up Time 15.8. Watchdog Timer 15.8.1. Features 15.8.2. Overview 15.9. Register Description 15.9.1. MCU Status Register 15.9.2. WDTCSR – Watchdog Timer Control Register 16. Interrupts 16.1. Interrupt Vectors in ATmega48/V 16.2. Interrupt Vectors in ATmega88/V 16.3. Interrupt Vectors in ATmega168/V 16.4. Register Description 16.4.1. Moving Interrupts Between Application and Boot Space 16.4.2. MCU Control Register 17. EXINT - External Interrupts 17.1. Pin Change Interrupt Timing 17.2. Register Description 17.2.1. External Interrupt Control Register A 17.2.2. External Interrupt Mask Register 17.2.3. External Interrupt Flag Register 17.2.4. Pin Change Interrupt Control Register 17.2.5. Pin Change Interrupt Flag Register 17.2.6. Pin Change Mask Register 2 17.2.7. Pin Change Mask Register 1 17.2.8. Pin Change Mask Register 0 18. I/O-Ports 18.1. Overview 18.2. Ports as General Digital I/O 18.2.1. Configuring the Pin 18.2.2. Toggling the Pin 18.2.3. Switching Between Input and Output 18.2.4. Reading the Pin Value 18.2.5. Digital Input Enable and Sleep Modes 18.2.6. Unconnected Pins 18.3. Alternate Port Functions 18.3.1. Alternate Functions of Port B 18.3.2. Alternate Functions of Port C 18.3.3. Alternate Functions of Port D 18.4. Register Description 18.4.1. MCU Control Register 18.4.2. Port B Data Register 18.4.3. Port B Data Direction Register 18.4.4. Port B Input Pins Address 18.4.5. Port C Data Register 18.4.6. Port C Data Direction Register 18.4.7. Port C Input Pins Address 18.4.8. Port D Data Register 18.4.9. Port D Data Direction Register 18.4.10. Port D Input Pins Address 19. TC0 - 8-bit Timer/Counter0 with PWM 19.1. Features 19.2. Overview 19.2.1. Definitions 19.2.2. Registers 19.3. Timer/Counter Clock Sources 19.4. Counter Unit 19.5. Output Compare Unit 19.5.1. Force Output Compare 19.5.2. Compare Match Blocking by TCNT1 Write 19.5.3. Using the Output Compare Unit 19.6. Compare Match Output Unit 19.6.1. Compare Output Mode and Waveform Generation 19.7. Modes of Operation 19.7.1. Normal Mode 19.7.2. Clear Timer on Compare Match (CTC) Mode 19.7.3. Fast PWM Mode 19.7.4. Phase Correct PWM Mode 19.8. Timer/Counter Timing Diagrams 19.9. Register Description 19.9.1. TC0 Control Register A 19.9.2. TC0 Control Register B 19.9.3. TC0 Interrupt Mask Register 19.9.4. General Timer/Counter Control Register 19.9.5. TC0 Counter Value Register 19.9.6. TC0 Output Compare Register A 19.9.7. TC0 Output Compare Register B 19.9.8. TC0 Interrupt Flag Register 20. TC1 - 16-bit Timer/Counter1 with PWM 20.1. Overview 20.2. Features 20.3. Block Diagram 20.4. Definitions 20.5. Registers 20.6. Accessing 16-bit Registers 20.6.1. Reusing the Temporary High Byte Register 20.7. Timer/Counter Clock Sources 20.8. Counter Unit 20.9. Input Capture Unit 20.9.1. Input Capture Trigger Source 20.9.2. Noise Canceler 20.9.3. Using the Input Capture Unit 20.10. Output Compare Units 20.10.1. Force Output Compare 20.10.2. Compare Match Blocking by TCNT1 Write 20.10.3. Using the Output Compare Unit 20.11. Compare Match Output Unit 20.11.1. Compare Output Mode and Waveform Generation 20.12. Modes of Operation 20.12.1. Normal Mode 20.12.2. Clear Timer on Compare Match (CTC) Mode 20.12.3. Fast PWM Mode 20.12.4. Phase Correct PWM Mode 20.12.5. Phase and Frequency Correct PWM Mode 20.13. Timer/Counter Timing Diagrams 20.14. Register Description 20.14.1. TC1 Control Register A 20.14.2. TC1 Control Register B 20.14.3. TC1 Control Register C 20.14.4. TC1 Counter Value Low byte 20.14.5. TC1 Counter High byte 20.14.6. Input Capture Register 1 Low byte 20.14.7. Input Capture Register 1 High byte 20.14.8. Output Compare Register 1 A Low byte 20.14.9. Output Compare Register 1 A High byte 20.14.10. Output Compare Register 1 B Low byte 20.14.11. Output Compare Register 1 B High byte 20.14.12. Timer/Counter 1 Interrupt Mask Register 20.14.13. TC1 Interrupt Flag Register 21. Timer/Counter 0, 1 Prescalers 21.1. Internal Clock Source 21.2. Prescaler Reset 21.3. External Clock Source 21.4. Register Description 21.4.1. General Timer/Counter Control Register 22. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation 22.1. Features 22.2. Overview 22.2.1. Definitions 22.2.2. Registers 22.3. Timer/Counter Clock Sources 22.4. Counter Unit 22.5. Output Compare Unit 22.5.1. Force Output Compare 22.5.2. Compare Match Blocking by TCNT2 Write 22.5.3. Using the Output Compare Unit 22.6. Compare Match Output Unit 22.6.1. Compare Output Mode and Waveform Generation 22.7. Modes of Operation 22.7.1. Normal Mode 22.7.2. Clear Timer on Compare Match (CTC) Mode 22.7.3. Fast PWM Mode 22.7.4. Phase Correct PWM Mode 22.8. Timer/Counter Timing Diagrams 22.9. Asynchronous Operation of Timer/Counter2 22.10. Timer/Counter Prescaler 22.11. Register Description 22.11.1. TC2 Control Register A 22.11.2. TC2 Control Register B 22.11.3. TC2 Counter Value Register 22.11.4. TC2 Output Compare Register A 22.11.5. TC2 Output Compare Register B 22.11.6. TC2 Interrupt Mask Register 22.11.7. TC2 Interrupt Flag Register 22.11.8. Asynchronous Status Register 22.11.9. General Timer/Counter Control Register 23. SPI – Serial Peripheral Interface 23.1. Features 23.2. Overview 23.3. SS Pin Functionality 23.3.1. Slave Mode 23.3.2. Master Mode 23.4. Data Modes 23.5. Register Description 23.5.1. SPI Control Register 0 23.5.2. SPI Status Register 0 23.5.3. SPI Data Register 0 24. USART - Universal Synchronous Asynchronous Receiver Transceiver 24.1. Features 24.2. Overview 24.3. Block Diagram 24.4. Clock Generation 24.4.1. Internal Clock Generation – The Baud Rate Generator 24.4.2. Double Speed Operation (U2Xn) 24.4.3. External Clock 24.4.4. Synchronous Clock Operation 24.5. Frame Formats 24.5.1. Parity Bit Calculation 24.6. USART Initialization 24.7. Data Transmission – The USART Transmitter 24.7.1. Sending Frames with 5 to 8 Data Bits 24.7.2. Sending Frames with 9 Data Bit 24.7.3. Transmitter Flags and Interrupts 24.7.4. Parity Generator 24.7.5. Disabling the Transmitter 24.8. Data Reception – The USART Receiver 24.8.1. Receiving Frames with 5 to 8 Data Bits 24.8.2. Receiving Frames with 9 Data Bits 24.8.3. Receive Compete Flag and Interrupt 24.8.4. Receiver Error Flags 24.8.5. Parity Checker 24.8.6. Disabling the Receiver 24.8.7. Flushing the Receive Buffer 24.9. Asynchronous Data Reception 24.9.1. Asynchronous Clock Recovery 24.9.2. Asynchronous Data Recovery 24.9.3. Asynchronous Operational Range 24.10. Multi-Processor Communication Mode 24.10.1. Using MPCMn 24.11. Examples of Baud Rate Setting 24.12. Register Description 24.12.1. USART I/O Data Register 0 24.12.2. USART Control and Status Register 0 A 24.12.3. USART Control and Status Register 0 B 24.12.4. USART Control and Status Register 0 C 24.12.5. USART Baud Rate 0 Register Low 24.12.6. USART Baud Rate 0 Register High 25. USARTSPI - USART in SPI Mode 25.1. Features 25.2. Overview 25.3. Clock Generation 25.4. SPI Data Modes and Timing 25.5. Frame Formats 25.5.1. USART MSPIM Initialization 25.6. Data Transfer 25.6.1. Transmitter and Receiver Flags and Interrupts 25.6.2. Disabling the Transmitter or Receiver 25.7. AVR USART MSPIM vs. AVR SPI 25.8. Register Description 26. TWI - 2-wire Serial Interface 26.1. Features 26.2. Two-Wire Serial Interface Bus Definition 26.2.1. TWI Terminology 26.2.2. Electrical Interconnection 26.3. Data Transfer and Frame Format 26.3.1. Transferring Bits 26.3.2. START and STOP Conditions 26.3.3. Address Packet Format 26.3.4. Data Packet Format 26.3.5. Combining Address and Data Packets into a Transmission 26.4. Multi-master Bus Systems, Arbitration, and Synchronization 26.5. Overview of the TWI Module 26.5.1. SCL and SDA Pins 26.5.2. Bit Rate Generator Unit 26.5.3. Bus Interface Unit 26.5.4. Address Match Unit 26.5.5. Control Unit 26.6. Using the TWI 26.7. Transmission Modes 26.7.1. Master Transmitter Mode 26.7.2. Master Receiver Mode 26.7.3. Slave Transmitter Mode 26.7.4. Slave Receiver Mode 26.7.5. Miscellaneous States 26.7.6. Combining Several TWI Modes 26.8. Multi-master Systems and Arbitration 26.9. Register Description 26.9.1. TWI Bit Rate Register 26.9.2. TWI Status Register 26.9.3. TWI (Slave) Address Register 26.9.4. TWI Data Register 26.9.5. TWI Control Register 26.9.6. TWI (Slave) Address Mask Register 27. AC - Analog Comparator 27.1. Overview 27.2. Analog Comparator Multiplexed Input 27.3. Register Description 27.3.1. ADC Control and Status Register B 27.3.2. Analog Comparator Control and Status Register 27.3.3. Digital Input Disable Register 1 28. ADC - Analog to Digital Converter 28.1. Features 28.2. Overview 28.3. Starting a Conversion 28.4. Prescaling and Conversion Timing 28.5. Changing Channel or Reference Selection 28.5.1. ADC Input Channels 28.5.2. ADC Voltage Reference 28.6. ADC Noise Canceler 28.6.1. Analog Input Circuitry 28.6.2. Analog Noise Canceling Techniques 28.6.3. ADC Accuracy Definitions 28.7. ADC Conversion Result 28.8. Temperature Measurement 28.9. Register Description 28.9.1. ADC Multiplexer Selection Register 28.9.2. ADC Control and Status Register A 28.9.3. ADC Data Register Low (ADLAR=0) 28.9.4. ADC Data Register High (ADLAR=0) 28.9.5. ADC Data Register Low (ADLAR=1) 28.9.6. ADC Data Register High (ADLAR=1) 28.9.7. ADC Control and Status Register B 28.9.8. Digital Input Disable Register 0 29. DBG - debugWIRE On-chip Debug System 29.1. Features 29.2. Overview 29.3. Physical Interface 29.4. Software Break Points 29.5. Limitations of debugWIRE 29.6. Register Description 29.6.1. debugWire Data Register 30. Self-Programming the Flash 30.1. Overview 30.1.1. Performing Page Erase by Store Program Memory (SPM) 30.1.2. Filling the Temporary Buffer (Page Loading) 30.1.3. Performing a Page Write 30.2. Addressing the Flash During Self-Programming 30.2.1. EEPROM Write Prevents Writing to SPMCSR 30.2.2. Reading the Fuse and Lock Bits from Software 30.2.3. Preventing Flash Corruption 30.2.4. Programming Time for Flash when Using SPM 30.2.5. Simple Assembly Code Example for a Boot Loader 30.3. Register Description 30.3.1. Store Program Memory Control and Status Register 31. BTLDR - Boot Loader Support – Read-While-Write Self-Programming 31.1. Features 31.2. Overview 31.3. Application and Boot Loader Flash Sections 31.3.1. Application Section 31.3.2. BLS – Boot Loader Section 31.4. Read-While-Write and No Read-While-Write Flash Sections 31.4.1. RWW – Read-While-Write Section 31.4.2. NRWW – No Read-While-Write Section 31.5. Boot Loader Lock Bits 31.6. Entering the Boot Loader Program 31.7. Addressing the Flash During Self-Programming 31.8. Self-Programming the Flash 31.8.1. Performing Page Erase by SPM 31.8.2. Filling the Temporary Buffer (Page Loading) 31.8.3. Performing a Page Write 31.8.4. Using the SPM Interrupt 31.8.5. Consideration While Updating Boot Loader Section (BLS) 31.8.6. Prevent Reading the RWW Section During Self-Programming 31.8.7. Setting the Boot Loader Lock Bits by SPM 31.8.8. EEPROM Write Prevents Writing to SPMCSR 31.8.9. Reading the Fuse and Lock Bits from Software 31.8.10. Reading the Signature Row from Software 31.8.11. Preventing Flash Corruption 31.8.12. Programming Time for Flash when Using SPM 31.8.13. Simple Assembly Code Example for a Boot Loader 31.8.14. ATmega88/V Boot Loader Parameters 31.8.15. ATmega168/V Boot Loader Parameters 31.9. Register Description 31.9.1. SPMCSR – Store Program Memory Control and Status Register 32. MEMPROG- Memory Programming 32.1. Program And Data Memory Lock Bits 32.2. Fuse Bits 32.2.1. Latching of Fuses 32.3. Signature Bytes 32.4. Calibration Byte 32.5. Page Size 32.6. Parallel Programming Parameters, Pin Mapping, and Commands 32.6.1. Signal Names 32.7. Parallel Programming 32.7.1. Enter Programming Mode 32.7.2. Considerations for Efficient Programming 32.7.3. Chip Erase 32.7.4. Programming the Flash 32.7.5. Programming the EEPROM 32.7.6. Reading the Flash 32.7.7. Reading the EEPROM 32.7.8. Programming the Fuse Low Bits 32.7.9. Programming the Fuse High Bits 32.7.10. Programming the Extended Fuse Bits 32.7.11. Programming the Lock Bits 32.7.12. Reading the Fuse and Lock Bits 32.7.13. Reading the Signature Bytes 32.7.14. Reading the Calibration Byte 32.7.15. Parallel Programming Characteristics 32.8. Serial Downloading 32.8.1. Serial Programming Pin Mapping 32.8.2. Serial Programming Algorithm 32.8.3. Serial Programming Instruction Set 32.8.4. SPI Serial Programming Characteristics 33. Electrical Characteristics 33.1. Absolute Maximum Ratings 33.2. Common DC Characteristics 33.2.1. DC Characteristics – Current Consumption 33.3. Speed Grades 33.4. Clock Characteristics 33.4.1. Calibrated Internal RC Oscillator Accuracy 33.4.2. External Clock Drive Waveforms 33.4.3. External Clock Drive 33.5. System and Reset Characteristics 33.6. SPI Timing Characteristics 33.7. Two-wire Serial Interface Characteristics 33.8. ADC Characteristics 33.9. Parallel Programming Characteristics 34. Typical Characteristics (TA = -40°C to 85°C) 34.1. Active Supply Current 34.2. Idle Supply Current 34.3. Supply Current of IO Modules 34.3.1. Example 34.3.2. Example 34.3.3. Example 34.4. Power-down Supply Current 34.5. Power-save Supply Current 34.6. Standby Supply Current 34.7. Pin Pull-Up 34.8. Pin Driver Strength 34.9. Pin Threshold and Hysteresis 34.10. Internal Oscillator Speed 34.11. BOD Threshold 34.12. Current Consumption of Peripheral Units 34.13. Current Consumption in Reset and Reset Pulsewidth 35. Register Summary 35.1. Note 36. Instruction Set Summary 37. Packaging Information 37.1. 32-pin 32A 37.2. 32-pin 32M1-A 37.3. 28-pin 28M1 37.4. 28-pin 28P3 38. Errata 38.1. Errata ATmega48/V 38.1.1. Rev. D 38.1.2. Rev. C 38.1.3. Rev. B 38.1.4. Rev. A 38.2. Errata ATmega88/V 38.2.1. Rev. D 38.2.2. Rev. B to C 38.2.3. Rev. A 38.3. Errata ATmega168/V 38.3.1. Rev. C 38.3.2. Rev. B 38.3.3. Rev. A 39. Datasheet Revision History 39.1. Rev. 2545W-11/16 39.2. Rev. 2545V-06/16 39.3. Rev. 2545U-11/15 39.4. Rev. 2545T-04/11 39.5. Rev. 2545S-07/10 39.6. Rev. 2545R-07/09 39.7. Rev. 2545Q-06/09 39.8. Rev. 2545P-02/09 39.9. Rev. 2545O-02/09 39.10. Rev. 2545N-01/09 39.11. Rev. 2545M-09/07 39.12. Rev. 2545L-08/07 39.13. Rev. 2545K-04/07 39.14. Rev. 2545J-12/06 39.15. Rev. 2545I-11/06 39.16. Rev. 2545H-10/06 39.17. Rev. 2545G-06/06 39.18. Rev. 2545F-05/05 39.19. Rev. 2545E-02/05 39.20. Rev. 2545D-07/04 39.21. Rev. 2545C-04/04 39.22. Rev. 2545B-01/04