Datasheet AT90USB1286, AT90USB1287, AT90USB646, AT90USB647 - Complete (Atmel)

Features
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High performance, low power AVR
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8-bit Microcontroller
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Advanced RISC architecture – 135 powerful instructions – most single clock cycle execution – 32 × 8 general purpose working registers – Fully static operation – Up to 16MIPS throughput at 16MHz – On-chip 2-cycle multiplier
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Non-volatile program and data memories – 64/128Kbytes of in-system self-programmable flash 8-bit Atmel • Endurance: 100,000 write/erase cycles Microcontroller – Optional Boot Code section with independent lock bits • USB boot loader programmed by default in the factory with • In-system programming by on-chip boot program hardware activated after reset 64/128Kbytes • True read-while-write operation • All supplied parts are pre-programed with a default USB bootloader of ISP Flash – 2K/4K (64K/128K flash version) bytes EEPROM • Endurance: 100,000 write/erase cycles and USB – 4K/8K (64K/128K flash version) bytes internal SRAM – Up to 64Kbytes optional external memory space Controller – Programming lock for software security
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JTAG (IEEE std. 1149.1 compliant) interface – Boundary-scan capabilities according to the JTAG standard AT90USB646 – Extensive on-chip debug support – Programming of flash, EEPROM, fuses, and lock bits through the JTAG interface AT90USB647
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USB 2.0 full-speed/low-speed device and on-the-go module – Complies fully with: AT90USB1286 – Universal serial bus specification REV 2.0 – On-the-go supplement to the USB 2.0 specification rev 1.0 AT90USB1287 – Supports data transfer rates up to 12Mbit/s and 1.5Mbit/s
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USB full-speed/low speed device module with interrupt on transfer completion – Endpoint 0 for control transfers: up to 64-bytes – Six programmable endpoints with in or out directions and with bulk, interrupt or isochronous transfers – Configurable endpoints size up to 256bytes in double bank mode – Fully independent 832bytes USB DPRAM for endpoint memory allocation – Suspend/resume interrupts – Power-on reset and USB bus reset – 48MHz PLL for full-speed bus operation – USB bus disconnection on microcontroller request
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USB OTG reduced host: – Supports host negotiation protocol (HNP) and session request protocol (SRP) for OTG dual-role devices – Provide status and control signals for software implementation of HNP and SRP – Provides programmable times required for HNP and SRP
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Peripheral features – Two 8-bit timer/counters with separate prescaler and compare mode – Two16-bit timer/counter with separate prescaler, compare- and capture mode
7593L–AVR–09/12 Document Outline Features 1. Pin configurations 2. Overview 2.1 Block diagram 2.2 Pin descriptions 2.2.1 VCC 2.2.2 GND 2.2.3 AVCC 2.2.4 Port A (PA7..PA0) 2.2.5 Port B (PB7..PB0) 2.2.6 Port C (PC7..PC0) 2.2.7 Port D (PD7..PD0) 2.2.8 Port E (PE7..PE0) 2.2.9 Port F (PF7..PF0) 2.2.10 D- 2.2.11 D+ 2.2.12 UGND 2.2.13 UVCC 2.2.14 UCAP 2.2.15 VBUS 2.2.16 RESET 2.2.17 XTAL1 2.2.18 XTAL2 2.2.19 AVCC 2.2.20 AREF 3. Resources 4. About code examples 5. AVR CPU core 5.1 Introduction 5.2 Architectural overview 5.3 ALU – Arithmetic Logic Unit 5.4 Status register 5.5 General purpose register file 5.5.1 The X-register, Y-register, and Z-register 5.6 Stack pointer 5.6.1 RAMPZ - Extended Z-pointer register for ELPM/SPM 5.7 Instruction execution timing 5.8 Reset and interrupt handling 5.8.1 Interrupt response time 6. Atmel AVR AT90USB64/128 memories 6.1 In-system re-programmable flash program memory 6.2 SRAM data memory 6.2.1 Data memory access times 6.3 EEPROM data memory 6.3.1 EEPROM Read/Write Access 6.3.2 EEARH and EEARL – The EEPROM Address Register 6.3.3 EEDR – The EEPROM Data Register 6.3.4 EECR – The EEPROM Control Register 6.3.5 Preventing EEPROM corruption 6.4 I/O memory 6.4.1 General purpose I/O registers 6.4.2 GPIOR2 – General purpose I/O Register 2 6.4.3 GPIOR1 – General purpose I/O Register 1 6.4.4 GPIOR0 – General purpose I/O Register 0 6.5 External memory interface 6.5.1 Overview 6.5.2 Using the external memory interface 6.5.3 Address latch requirements 6.5.4 Pull-up and bus-keeper 6.5.5 Timing 6.5.6 XMCRA – External Memory Control Register A 6.5.7 XMCRB – External Memory Control Register B 6.5.8 Using all locations of external memory smaller than 64KB 6.5.9 Using all 64KB locations of external memory 7. System clock and clock options 7.1 Clock systems and their distribution 7.1.1 CPU Clock – clkCPU 7.1.2 I/O Clock – clkI/O 7.1.3 Flash Clock – clkFLASH 7.1.4 Asynchronous Timer Clock – clkASY 7.1.5 ADC Clock – clkADC 7.1.6 USB Clock – clkUSB 7.2 Clock sources 7.2.1 Default clock source 7.2.2 Clock startup sequence 7.3 Low power crystal oscillator 7.4 Low frequency crystal oscillator 7.5 Calibrated internal RC oscillator 7.5.1 OSCCAL – Oscillator Calibration Register 7.6 External clock 7.7 Clock output buffer 7.8 Timer/counter oscillator 7.9 System clock prescaler 7.9.1 CLKPR – Clock Prescale Register 7.10 PLL 7.10.1 Internal PLL for USB interface 7.10.2 PLLCSR – PLL Control and Status Register 8. Power management and sleep modes 8.0.1 SMCR – Sleep Mode Control Register 8.1 Idle mode 8.2 ADC noise reduction mode 8.3 Power-down mode 8.4 Power-save mode 8.5 Standby mode 8.6 Extended Standby mode 8.7 Power Reduction Register 8.7.1 PRR0 – Power Reduction Register 0 8.7.2 PRR1 – Power Reduction Register 1 8.8 Minimizing power consumption 8.8.1 Analog to digital converter 8.8.2 Analog comparator 8.8.3 Brown-out detector 8.8.4 Internal voltage reference 8.8.5 Watchdog timer 8.8.6 Port pins 8.8.7 On-chip debug system 9. System control and reset 9.1 Resetting the AVR 9.2 Reset sources 9.3 Power-on reset 9.4 External reset 9.5 Brown-out detection 9.6 Watchdog reset 9.6.1 MCUSR – MCU Status Register 9.7 Internal voltage reference 9.7.1 Voltage reference enable signals and start-up time 9.8 Watchdog timer 9.8.1 WDTCSR – Watchdog Timer Control Register 10. Interrupts 10.1 Interrupt vectors in AT90USB64/128 10.1.1 Moving interrupts between application and boot space 10.1.2 MCUCR – MCU Control Register 11. I/O-ports 11.1 Introduction 11.2 Ports as general digital I/O 11.2.1 Configuring the pin 11.2.2 Toggling the pin 11.2.3 Switching between input and output 11.2.4 Reading the pin value 11.2.5 Digital input enable and sleep modes 11.2.6 Unconnected pins 11.3 Alternate port functions 11.3.1 MCUCR – MCU Control Register 11.3.2 Alternate functions of Port A 11.3.3 Alternate functions of Port B 11.3.4 Alternate functions of Port C 11.3.5 Alternate Functions of Port D 11.3.6 Alternate functions of Port E 11.3.7 Alternate functions of Port F 11.4 Register description for I/O-ports 11.4.1 PORTA – Port A Data Register 11.4.2 DDRA – Port A Data Direction Register 11.4.3 PINA – Port A Input Pins Address 11.4.4 PORTB – Port B Data Register 11.4.5 DDRB – Port B Data Direction Register 11.4.6 PINB – Port B Input Pins Address 11.4.7 PORTC – Port C Data Register 11.4.8 DDRC – Port C Data Direction Register 11.4.9 PINC – Port C Input Pins Address 11.4.10 PORTD – Port D Data Register 11.4.11 DDRD – Port D Data Direction Register 11.4.12 PIND – Port D Input Pins Address 11.4.13 PORTE – Port E Data Register 11.4.14 DDRE – Port E Data Direction Register 11.4.15 PINE – Port E Input Pins Address 11.4.16 PORTF – Port F Data Register 11.4.17 DDRF – Port F Data Direction Register 11.4.18 PINF – Port F Input Pins Address 12. External interrupts 12.0.1 EICRA – External Interrupt Control Register A 12.0.2 EICRB – External Interrupt Control Register B 12.0.3 EIMSK – External Interrupt Mask Register 12.0.4 EIFR – External Interrupt Flag Register 12.0.5 PCICR – Pin Change Interrupt Control Register 12.0.6 PCIFR – Pin Change Interrupt Flag Register 12.0.7 PCMSK0 – Pin Change Mask Register 0 13. Timer/Counter0, Timer/Counter1, and Timer/Counter3 prescalers 13.1 Internal clock source 13.2 Prescaler reset 13.3 External clock source 13.4 GTCCR – General Timer/Counter Control Register 14. 8-bit Timer/Counter0 with PWM 14.1 Overview 14.1.1 Registers 14.1.2 Definitions 14.2 Timer/Counter clock sources 14.3 Counter unit 14.4 Output compare unit 14.4.1 Force output compare 14.4.2 Compare match blocking by TCNT0 write 14.4.3 Using the output compare unit 14.5 Compare Match Output Unit 14.5.1 Compare output mode and waveform generation 14.6 Modes of operation 14.6.1 Normal mode 14.6.2 Clear Timer on Compare Match (CTC) mode 14.6.3 Fast PWM mode 14.6.4 Phase correct PWM mode 14.7 Timer/Counter timing diagrams 14.8 8-bit Timer/Counter register description 14.8.1 TCCR0A – Timer/Counter Control Register A 14.8.2 TCCR0B – Timer/Counter Control Register B 14.8.3 TCNT0 – Timer/Counter Register 14.8.4 OCR0A – Output Compare Register A 14.8.5 OCR0B – Output Compare Register B 14.8.6 TIMSK0 – Timer/Counter Interrupt Mask Register 14.8.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register 15. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) 15.1 Overview 15.1.1 Registers 15.1.2 Definitions 15.2 Accessing 16-bit registers 15.2.1 Reusing the Temporary High Byte register 15.3 Timer/Counter clock sources 15.4 Counter unit 15.5 Input Capture unit 15.5.1 Input Capture Trigger Source 15.5.2 Noise Canceler 15.5.3 Using the Input Capture unit 15.6 Output Compare units 15.6.1 Force Output Compare 15.6.2 Compare Match Blocking by TCNTn write 15.6.3 Using the Output Compare unit 15.7 Compare Match Output unit 15.7.1 Compare Output mode and Waveform generation 15.8 Modes of operation 15.8.1 Normal mode 15.8.2 Clear Timer on Compare Match (CTC) mode 15.8.3 Fast PWM mode 15.8.4 Phase correct PWM mode 15.8.5 Phase and frequency correct PWM mode 15.9 Timer/Counter timing diagrams 15.10 16-bit Timer/Counter register description 15.10.1 TCCR1A – Timer/Counter1 Control Register A 15.10.2 TCCR3A – Timer/Counter3 Control Register A 15.10.3 TCCR1B – Timer/Counter1 Control Register B 15.10.4 TCCR3B – Timer/Counter3 Control Register B 15.10.5 TCCR1C – Timer/Counter1 Control Register C 15.10.6 TCCR3C – Timer/Counter3 Control Register C 15.10.7 TCNT1H and TCNT1L – Timer/Counter1 15.10.8 TCNT3H and TCNT3L – Timer/Counter3 15.10.9 OCR1AH and OCR1AL – Output Compare Register 1 A 15.10.10 OCR1BH and OCR1BL – Output Compare Register 1 B 15.10.11 OCR1CH and OCR1CL – Output Compare Register 1 C 15.10.12 OCR3AH and OCR3AL – Output Compare Register 3 A 15.10.13 OCR3BH and OCR3BL – Output Compare Register 3 B 15.10.14 OCR3CH and OCR3CL – Output Compare Register 3 C 15.10.15 ICR1H and ICR1L – Input Capture Register 1 15.10.16 ICR3H and ICR3L – Input Capture Register 3 15.10.17 TIMSK1 – Timer/Counter1 Interrupt Mask Register 15.10.18 TIMSK3 – Timer/Counter3 Interrupt Mask Register 15.10.19 TIFR1 – Timer/Counter1 Interrupt Flag Register 15.10.20 TIFR3 – Timer/Counter3 Interrupt Flag Register 16. 8-bit Timer/Counter2 with PWM and asynchronous operation 16.1 Overview 16.1.1 Registers 16.1.2 Definitions 16.2 Timer/Counter clock sources 16.3 Counter unit 16.4 Output Compare unit 16.4.1 Force output compare 16.4.2 Compare Match Blocking by TCNT2 Write 16.4.3 Using the Output Compare unit 16.5 Compare Match Output unit 16.5.1 Compare Output mode and Waveform generating 16.6 Modes of operation 16.6.1 Normal mode 16.6.2 Clear Timer on Compare Match (CTC) mode 16.6.3 Fast PWM mode 16.6.4 Phase correct PWM mode 16.7 Timer/Counter timing diagrams 16.8 8-bit Timer/Counter register description 16.8.1 TCCR2A – Timer/Counter Control Register A 16.8.2 TCCR2B – Timer/Counter Control Register B 16.8.3 TCNT2 – Timer/Counter Register 16.8.4 OCR2A – Output Compare Register A 16.8.5 OCR2B – Output Compare Register B 16.9 Asynchronous operation of the Timer/Counter 16.9.1 ASSR – Asynchronous Status Register 16.9.2 Asynchronous operation of Timer/Counter2 16.9.3 TIMSK2 – Timer/Counter2 Interrupt Mask Register 16.9.4 TIFR2 – Timer/Counter2 Interrupt Flag Register 16.10 Timer/Counter prescaler 16.10.1 GTCCR – General Timer/Counter Control Register 17. Output Compare Modulator (OCM1C0A) 17.1 Overview 17.2 Description 17.2.1 Timing example 18. SPI – Serial Peripheral Interface 18.1 SS Pin Functionality 18.1.1 Slave Mode 18.1.2 Master mode 18.1.3 SPCR – SPI Control Register 18.1.4 SPSR – SPI Status Register 18.1.5 SPDR – SPI Data Register 18.2 Data modes 19. USART 19.1 Overview 19.2 Clock generation 19.2.1 Internal Clock Generation – The Baud Rate generator 19.2.2 Double speed operation (U2Xn) 19.2.3 External clock 19.2.4 Synchronous clock operation 19.3 Frame formats 19.3.1 Parity bit calculation 19.4 USART initialization 19.5 Data transmission – The USART transmitter 19.5.1 Sending frames with 5 to 8 data bits 19.5.2 Sending frames with 9 data bits 19.5.3 Transmitter flags and interrupts 19.5.4 Parity Generator 19.5.5 Disabling the transmitter 19.6 Data reception – The USART receiver 19.6.1 Receiving frames with 5 to 8 data bits 19.6.2 Receiving frames with 9 data bits 19.6.3 Receive compete flag and interrupt 19.6.4 Receiver error flags 19.6.5 Parity Checker 19.6.6 Disabling the Receiver 19.6.7 Flushing the receive buffer 19.7 Asynchronous data reception 19.7.1 Asynchronous clock recovery 19.7.2 Asynchronous data recovery 19.7.3 Asynchronous Operational Range 19.8 Multi-processor Communication mode 19.8.1 Using MPCMn 19.9 USART register description 19.9.1 UDRn – USART I/O Data Register n 19.9.2 UCSRnA – USART Control and Status Register A 19.9.3 UCSRnB – USART Control and Status Register n B 19.9.4 UCSRnC – USART Control and Status Register n C 19.9.5 UBRRLn and UBRRHn – USART baud rate registers 19.10 Examples of baud rate setting 20. USART in SPI mode 20.1 Overview 20.2 Clock generation 20.3 SPI data modes and timing 20.4 Frame formats 20.4.1 USART MSPIM initialization 20.5 Data transfer 20.5.1 Transmitter and receiver flags and interrupts 20.5.2 Disabling the transmitter or receiver 20.6 USART MSPIM register description 20.6.1 UDRn – USART MSPIM I/O data register 20.6.2 UCSRnA – USART MSPIM Control and Status Register n A 20.6.3 UCSRnB – USART MSPIM Control and Status Register n B 20.6.4 UCSRnC – USART MSPIM Control and Status Register n C 20.6.5 UBRRnL and UBRRnH – USART MSPIM Baud Rate Registers 20.7 AVR USART MSPIM vs. AVR SPI 21. 2-wire serial interface 21.1 Features 21.2 2-wire Serial Interface bus definition 21.2.1 TWI terminology 21.2.2 Electrical interconnection 21.3 Data transfer and frame format 21.3.1 Transferring bits 21.3.2 START and STOP conditions 21.3.3 Address packet format 21.3.4 Data packet format 21.3.5 Combining address and data packets into a transmission 21.4 Multi-master bus systems, arbitration and synchronization 21.5 Overview of the TWI module 21.5.1 SCL and SDA pins 21.5.2 Bit Rate Generator unit 21.5.3 Bus Interface unit 21.5.4 Address Match unit 21.5.5 Control unit 21.6 TWI register description 21.6.1 TWBR – TWI Bit Rate Register 21.6.2 TWCR – TWI Control Register 21.6.3 TWSR – TWI Status Register 21.6.4 TWDR – TWI Data Register 21.6.5 TWAR – TWI (Slave) Address Register 21.6.6 TWAMR – TWI (Slave) Address Mask Register 21.7 Using the TWI 21.8 Transmission modes 21.8.1 Master Transmitter Mode 21.8.2 Master Receiver mode 21.8.3 Slave Receiver mode 21.8.4 Slave Transmitter mode 21.8.5 Miscellaneous states 21.8.6 Combining several TWI modes 21.9 Multi-master systems and arbitration 22. USB controller 22.1 Features 22.2 Block diagram 22.3 Typical application implementation 22.3.1 Device mode 22.3.1.1 Bus powered device 22.3.1.2 Self powered device 22.3.2 Host / OTG mode 22.3.3 Design guidelines 22.4 General operating modes 22.4.1 Introduction 22.4.2 Power-on and reset 22.4.3 Interrupts 22.5 Power modes 22.5.1 Idle mode 22.5.2 Power down 22.5.3 Freeze clock 22.6 Speed control 22.6.1 Device mode 22.6.2 Host mode 22.7 Memory management 22.8 PAD suspend 22.9 OTG timers customizing 22.10 Plug-in detection 22.10.1 Peripheral mode 22.10.2 Host mode 22.11 ID detection 22.12 Registers description 22.12.1 USB general registers 22.13 USB Software Operating modes 23. USB device operating modes 23.1 Introduction 23.2 Power-on and reset 23.3 Endpoint reset 23.4 USB reset 23.5 Endpoint selection 23.6 Endpoint activation 23.7 Address setup 23.8 Suspend, wake-up and resume 23.9 Detach 23.10 Remote Wake-up 23.11 STALL request 23.11.1 Special consideration for control endpoints 23.11.2 STALL handshake and retry mechanism 23.12 CONTROL endpoint management 23.12.1 Control write 23.12.2 Control read 23.13 OUT endpoint management 23.13.1 Overview 23.13.2 Detailed description 23.14 IN endpoint management 23.14.1 Overview 23.14.2 Detailed description 23.14.2.1 Abort 23.15 Isochronous mode 23.15.1 Underflow 23.15.2 CRC error 23.16 Overflow 23.17 Interrupts 23.18 Registers 23.18.1 USB device general registers 23.18.2 USB device endpoint registers 24. USB host operating modes 24.1 Pipe description 24.2 Detach 24.3 Power-on and reset 24.4 Device detection 24.5 Pipe selection 24.6 Pipe configuration 24.7 USB reset 24.8 Address setup 24.9 Remote wake-up detection 24.10 USB pipe reset 24.11 Pipe data access 24.12 Control pipe management 24.13 OUT pipe management 24.14 IN Pipe management 24.14.1 CRC error (isochronous only) 24.15 Interrupt system 24.16 Registers 24.16.1 General USB host registers 24.16.2 USB Host Pipe registers 25. Analog Comparator 25.0.1 ADCSRB – ADC Control and Status Register B 25.0.2 ACSR – Analog Comparator Control and Status Register 25.1 Analog Comparator multiplexed input 25.1.1 DIDR1 – Digital Input Disable Register 1 26. ADC – Analog to Digital Converter 26.1 Features 26.2 Overview 26.3 Operation 26.4 Starting a conversion 26.5 Prescaling and conversion timing 26.5.1 Differential channels 26.6 Changing channel or reference selection 26.6.1 ADC input channels 26.6.2 ADC voltage reference 26.7 ADC noise canceler 26.7.1 Analog input circuitry 26.7.2 Analog noise canceling techniques 26.7.3 Offset compensation schemes 26.7.4 ADC accuracy definitions 26.8 ADC conversion result 26.9 ADC register description 26.9.1 ADMUX – ADC Multiplexer Selection Register 26.9.2 ADCSRA – ADC Control and Status Register A 26.9.3 ADCL and ADCH – The ADC data register 26.9.3.1 ADLAR = 0 26.9.3.2 ADLAR = 1 26.9.4 ADCSRB – ADC Control and Status Register B 26.9.5 DIDR0 – Digital Input Disable Register 0 27. JTAG interface and on-chip debug system 27.0.1 Features 27.1 Overview 27.2 TAP – Test Access Port 27.3 TAP Controller 27.4 Using the Boundary-scan chain 27.5 Using the on-chip debug system 27.6 On-chip debug specific JTAG instructions 27.6.1 PRIVATE0; 0x8 27.6.2 PRIVATE1; 0x9 27.6.3 PRIVATE2; 0xA 27.6.4 PRIVATE3; 0xB 27.7 On-chip Debug related Register in I/O memory 27.7.1 OCDR – On-chip Debug Register 27.8 Using the JTAG programming capabilities 27.9 Bibliography 28. IEEE 1149.1 (JTAG) boundary-scan 28.1 Features 28.2 System overview 28.3 Data registers 28.3.1 Bypass register 28.3.2 Device Identification register 28.3.2.1 Version 28.3.2.2 Part number 28.3.2.3 Manufacturer ID 28.3.3 Reset register 28.3.4 Boundary-scan Chain 28.4 Boundary-scan specific JTAG instructions 28.4.1 EXTEST; 0x0 28.4.2 IDCODE; 0x1 28.4.3 SAMPLE_PRELOAD; 0x2 28.4.4 AVR_RESET; 0xC 28.4.5 BYPASS; 0xF 28.5 Boundary-scan Related Register in I/O memory 28.5.1 MCUCR – MCU Control Register 28.5.2 MCUSR – MCU Status Register 28.6 Boundary-scan chain 28.6.1 Scanning the digital port pins 28.6.2 Scanning the RESET pin 28.7 Atmel AT90USB64/128 Boundary-scan order 28.8 Boundary-scan description language files 29. Boot Loader support – read-while-write self-programming 29.1 Boot Loader features 29.2 Application and Boot Loader flash sections 29.2.1 Application section 29.2.2 BLS – Boot Loader section 29.3 Read-while-write and no read-while-write flash sections 29.3.1 RWW – Read-While-Write section 29.3.2 NRWW – No Read-While-Write section 29.4 Boot Loader lock bits 29.5 Entering the Boot Loader program 29.5.1 Regular application conditions. 29.5.2 Boot Reset fuse 29.5.3 External hardware conditions 29.5.4 SPMCSR – Store Program Memory Control and Status Register 29.6 Addressing the flash during self-programming 29.7 Self-programming the flash 29.7.1 Performing page erase by SPM 29.7.2 Filling the Temporary Buffer (page loading) 29.7.3 Performing a Page Write 29.7.4 Using the SPM interrupt 29.7.5 Consideration while updating BLS 29.7.6 Prevent reading the RWW section during self-programming 29.7.7 Setting the Boot Loader Lock bits by SPM 29.7.8 EEPROM Write prevents writing to SPMCSR 29.7.9 Reading the Fuse and Lock bits from software 29.7.10 Reading the Signature Row from software 29.7.11 Preventing flash corruption 29.7.12 Programming time for flash when using SPM 29.7.13 Simple Assembly Code example for a Boot Loader 29.7.14 Atmel AT90USB64/128 Boot Loader parameters 30. Memory programming 30.1 Program and data memory lock bits 30.2 Fuse bits 30.2.1 Latching of fuses 30.3 Signature bytes 30.4 Calibration byte 30.5 Parallel programming parameters, pin mapping, and commands 30.5.1 Signal names 30.6 Parallel programming 30.6.1 Enter programming mode 30.6.2 Considerations for efficient programming 30.6.3 Chip erase 30.6.4 Programming the Flash 30.6.5 Programming the EEPROM 30.6.6 Reading the Flash 30.6.7 Reading the EEPROM 30.6.8 Programming the Fuse Low bits 30.6.9 Programming the Fuse High bits 30.6.10 Programming the Extended Fuse bits 30.6.11 Programming the Lock bits 30.6.12 Reading the Fuse and Lock bits 30.6.13 Reading the Signature bytes 30.6.14 Reading the Calibration byte 30.6.15 Parallel programming characteristics 30.7 Serial downloading 30.8 Serial programming pin mapping 30.8.1 Serial programming algorithm 30.8.2 Serial programming characteristics 30.9 Programming via the JTAG interface 30.9.1 Programming specific JTAG instructions 30.9.2 AVR_RESET (0xC) 30.9.3 PROG_ENABLE (0x4) 30.9.4 PROG_COMMANDS (0x5) 30.9.5 PROG_PAGELOAD (0x6) 30.9.6 PROG_PAGEREAD (0x7) 30.9.7 Data Registers 30.9.8 Reset Register 30.9.9 Programming Enable Register 30.9.10 Programming Command Register 30.9.11 Flash Data Byte Register 30.9.12 Programming algorithm 30.9.13 Entering Programming mode 30.9.14 Leaving Programming mode 30.9.15 Performing Chip Erase 30.9.16 Programming the Flash 30.9.17 Reading the Flash 30.9.18 Programming the EEPROM 30.9.19 Reading the EEPROM 30.9.20 Programming the Fuses 30.9.21 Programming the Lock Bits 30.9.22 Reading the Fuses and Lock Bits 30.9.23 Reading the Signature Bytes 30.9.24 Reading the Calibration Byte 31. Electrical characteristics for Atmel AT90USB64/128 31.1 Absolute maximum ratings* 31.2 DC characteristics 31.3 External clock drive waveforms 31.4 External clock drive 31.5 Maximum speed vs. VCC 31.6 2-wire serial interface characteristics 31.7 SPI timing characteristics 31.8 Hardware boot entrance timing characteristics 31.9 ADC characteristics 31.10 External data memory timing 32. Atmel AT90USB64/128 typical characteristics 32.1 Input voltage levels 32.2 Output voltage levels 32.3 Power-down supply current 32.4 Power-save supply current 32.5 Idle supply current 32.6 Active supply current 32.7 Reset supply current 32.8 I/O pull-up current 32.9 Bandgap voltage 32.10 Internal ARef voltage 32.11 USB regulator 32.12 BOD levels 32.13 Watchdog timer frequency 32.14 Internal RC oscillator frequency 32.15 Power-on reset 33. Register summary 34. Instruction set summary 35. Ordering information 35.1 Atmel AT90USB646 35.2 Atmel AT90USB647 35.3 Atmel AT90USB1286 35.4 Atmel AT90USB1287 36. Packaging information 36.1 TQFP64 36.2 QFN64 37. Errata 37.1 Atmel AT90USB1287/6 errata 37.1.1 AT90USB1287/6 errata history 37.1.2 AT90USB1287/6 first release 37.1.3 Atmel AT90USB1287/6 second release 37.1.4 Atmel AT90USB1287/6 Third Release 37.1.5 Atmel AT90USB1287/6 Fourth Release 37.2 Atmel AT90USB646/7 errata 37.2.1 AT90USB646/7 errata history TBD 37.2.2 AT90USB646/7 first release. 37.2.3 Atmel AT90USB646/7 Second Release. 38. Datasheet revision history for Atmel AT90USB64/128 38.1 Changes from 7593A to 7593B 38.2 Changes from 7593B to 7593C 38.3 Changes from 7593C to 7593D 38.4 Changes from 7593D to 7593E 38.5 Changes from 7593E to 7593F 38.6 Changes from 7593F to 7593G 38.7 Changes from 7593G to 7593H 38.8 Changes from 7593H to 7593I 38.9 Changes from 7593I to 7593J 38.10 Changes from 7593J to 7593K 38.11 Changes from 7593K to 7593L Table of contents