Figure 4. The AT90S8515 AVR RISC Architecture Data Bus 8-bit 4K x 16 Program Memory Program Counter Status and Test 32 x 8 General Purpose Registers Control Lines Indirect Addressing Instruction Decoder Direct Addressing Instruction Register Control Registers Interrupt Unit SPI Unit Serial UART ALU 8-bit Timer/Counter 512 x 8 Data SRAM 512 x 8 EEPROM 16-bit Timer/Counter with PWM Watchdog Timer Analog Comparator 32 I/O Lines A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. 8 AT90S8515 0841G–09/01
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