Datasheet AT90S2333, AT90LS2333, AT90S4433, AT90LS4433 - Preliminary (Atmel)

Features
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High-performance and Low-power AVR® 8-bit RISC Architecture – 118 Powerful Instructions - Most Single Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 8 MIPS Throughput at 8 MHz
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Data and Nonvolatile Program Memory – 2K/4K Bytes of In-System Programmable Flash Endurance 1,000 Write/Erase Cycles – 128 Bytes of SRAM – 128/256 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles 8-bit – Programming Lock for Flash Program and EEPROM Data Security
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Peripheral Features Microcontroller – One 8-bit Timer/Counter with Separate Prescaler – Expanded 16-bit Timer/Counter with Separate Prescaler, with 2K/4K bytes Compare, Capture Modes and 8-, 9- or 10-bit PWM – On-chip Analog Comparator – Programmable Watchdog Timer with Separate On-chip Oscillator In-System – Programmable UART – 6-channel, 10-bit ADC Programmable – Master/Slave SPI Serial Interface
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Special Microcontroller Features Flash – Brown-Out Reset Circuit – Enhanced Power-on Reset Circuit – Low-Power Idle and Power Down Modes – External and Internal Interrupt Sources AT90S2333
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Specifications – Low-power, High-speed CMOS Process Technology AT90LS2333 – Fully Static Operation
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Power Consumption at 4 MHz, 3V, 25
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C AT90S4433 – Active: 3.4 mA – Idle Mode: 1.4 mA AT90LS4433 – Power Down Mode: <1 µA
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I/O and Packages – 20 Programmable I/O Lines – 28-pin PDIP and 32-pin TQFP
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Operating Voltage Preliminary – 2.7V - 6.0V (AT90LS2333 and AT90LS4433) – 4.0V - 6.0V (AT90S2333 and AT90S4433)
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Speed Grades – 0 - 4 MHz (AT90LS2333 and AT90LS4433) – 0 - 8 MHz (AT90S2333 and AT90S4433) Pin Configurations
TQFP Top View PDIP RESET 1 28 PC5 (ADC5) (RXD) PD0 2 27 PC4 (ADC4) PD2 (INT0) PD1 (TXD) PD0 (RDX) RESET PC5 (ADC5) PC4 (ADC4) PC3 (ADC3) PC2 (ADC2) (TXD) PD1 3 26 PC3 (ADC3) 32 31 30 29 28 27 26 25 (INT0) PD2 4 25 PC2 (ADC2) (INT1) PD3 5 24 PC1 (ADC1) (INT1) PD3 1 24 PC1 (ADC1) (T0) PD4 2 23 PC0 (ADC0) (T0) PD4 6 23 PC0 (ADC0) NC 3 22 NC VCC 7 22 AGND VCC 4 21 AGND GND 8 21 AREF GND 5 20 AREF XTAL1 9 20 AVCC NC 6 19 NC XTAL2 10 19 PB5 (SCK) XTAL1 7 18 AVCC XTAL2 8 17 PB5 (SCK) (T1) PD5 11 18 PB4 (MISO) (AIN0) PD6 12 17 PB3 (MOSI) 9 10 11 12 13 14 15 16 (AIN1) PD7 13 16 PB2 (SS) Rev. 1042DS–04/99 (ICP) PB0 14 15 PB1 (OC1) (T1) PD5 (ICP) PB0 (SS) PB2 (AIN0) PD6 (AIN1) PD7 (OC1) PB1 (MOS1) PB3 (MOS0) PB4 Note: This is a summary document. For the complete 103 page document, please visit our Web site at www.atmel.com or e-m
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ail at [email protected] and request literature #1042D. Document Outline Features Description Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) Port C (PC5..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Architectural Overview Register Summary (Continued) Instruction Set Summary (Continued) Ordering Information Pin Configurations