Datasheet LTC4013 (Analog Devices) - 4

LTC4013
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). DCIN, VIN, VIN_S = 18V, ENAB = 1.4V, SYNC = 0V unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Error Amp
Error Amp Transconductance ∆IITH/∆(VSENSE–VBAT) VITH = 1.8V 1300 1800 2300 µmho Error Amp Current Source VITH =1.8V, VFB = 2.0V, (Float) MODE1 = H, MODE2 = L –6.5 –10 –13.5 µA Error Amp Current Sink VITH =1.8V, VFB = 2.4V, (Float) MODE1 = H, MODE2 = L 18 27 35 µA
Current Sense (all measured as VSENSE – VBAT unless otherwise noted)
Maximum Charging Sense Resistor Voltage In Absorption, Float, Li-Ion Charge, BAT = 14V l 48 50 52 mV Equalization and Low Battery Charging Sense BAT = 14V l 8 10 12.5 mV Resistor Voltage Current Sense C/10 Threshold Termination when TMR = 0 l 2.0 4.6 7.0 mV Constant Voltage (CV) Threshold VFB(ABS,EQ) – VFB, Timeout Initiation with Cap on TMR l 15.6 24.5 mV Overcurrent Charging Turnoff l 100 106 mV ISMON Fullscale Output Voltage VSENSE – VBAT = 50mV 1.00 V SENSE Input UVLO VSENSE Rising (Charging Enabled) l 1.86 1.97 2.07 V SENSE Input UVLO Hysteresis VSENSE Rising to Falling (Charging Disabled) 100 mV
Configuration Pins
MODE1, MODE2 Pin, Low Threshold l 0.8 V MODE1, MODE2 Pin, Mid Threshold l 1.3 1.8 V MODE1, MODE2 Pin, High Threshold l 2.5 V
Timer
TMR Oscillator High Threshold 1.5 V TMR Oscillator Low Threshold 0.97 V Safety Timer Turn on Voltage TMR Voltage Rising l 0.45 0.5 0.65 V Safety Timer Turn on Hysteresis Voltage 250 mV TMR Source/Sink Current TMR = 1.25V 8.5 10.0 11.5 μA TMR Pin Period CTMR = 0.2µF 20.8 ms End of Charge Termination Time, tEOC CTMR = 0.2µF 3.03 hr Equalization Charge Termination Time CTMR = 0.2µF, MODE1 = M, H 0.379 hr CTMR = 0.2µF, MODE1 = L 0.758 hr
INTVCC Regulator (INTVCC Pin)
INTVCC Regulation Voltage 5.00 V INTVCC Dropout Voltage DCIN = 4.5V, INTVCC = 5mA 4.46 V INTVCC Supply Short-Circuit Current INTVCC = 0V 100 175 mA
NMOS FET Drivers
Non-Overlap Time TG to BG 40 ns Non-Overlap Time BG to TG 74 ns Minimum On-Time BG 38 ns Minimum On-Time TG 37 ns Minimum Off-Time BG 65 ns Top Gate Driver Switch On Resistance BST – SW = 5V, Pull Up 2.3 Ω BST – SW = 5V, Pull Down 1.3 Ω Bottom Gate Driver Switch On Resistance INTVCC = 5V, Pull Up 2.3 Ω INTVCC = 5V, Pull Down 1 Ω 4013fa 4