Datasheet LTC4100 (Analog Devices) - 9

LTC4100
block DiagraM
C4 R4 VBAT 0.01µF 3k 100Ω V BAT SET – VBAT 18 22 + 11.67µA C5, 0.1µF 11-BIT RSENSE V GND DAC – 12 20µF CA1 3k DCIN CSP + 21 1.28V 0V OSCILLATOR CSP 9k WATCHDOG Ω SYSTEM DETECT t BUFFERED ON – gm = 1m ITH LOAD 20µF EA ÷5 1.19V + CLP +– L1 TGATE S CSP Q2 1 Q I R CMP PWM I – REV 17mV LOGIC I D1 BGATE + DC Q3 3 20 C8 R1 PGND – 2 0.068µF 100mV Ω CA2 CLN gm = 1.5m Ω C9 23 + + 1.19V R gm = 1m I CL TH CLP CL1 19 24 – 10-BIT R5, 6.04k C7 DCIN 5 I 0.0015µF DAC C6, 0.12µF 5.8V INFET 10 ACP Q1 4 CLP DCDIV 11 V V IN IN CHGEN 6 R10 V R11 DD 1.2V C1, 0.1µF 10µA SMBALERT 7 17 VDD TO SMBUS POWER SUPPLY SMBus TO HOST AND BATTERY INTERFACE SDA 8 AND CONTROL ILIM LIMIT 13 SCL 9 1.13k DECODER VLIM 14 16 THA THERMISTER INTERFACE 15 RVLIM RILIM THB 54.9k 10k
Figure 2
4100fc For more information www.linear.com/LTC4100 9