Datasheet LTC2051, LTC2052 (Analog Devices) - 9

LTC2051/LTC2052
U TYPICAL APPLICATIO Obtaining Ultralow VOS Drift and Low Noise
+ 5 + 2 7 – 1/2 LTC2051 R4 1 6 1/2 LTC2051 – 3 + 5V C1 R5 OUT 20512 F01 C2 R1 R2 R3 1 3 + 8 6 A1 OUT 2 – –
A1 R1 R2 R3 R4 R5 C1 C2 eIN (DC – 1Hz) eIN (DC – 10Hz)
LT1677 2.49k 3.01k 340k 10k 100k 0.01μF 0.001μF 0.15μVP-P 0.2μVP-P LT1012 750Ω 57Ω 250k 10k 100k 0.01μF 0.001μF 0.3μVP-P 0.4μVP-P
U PACKAGE DESCRIPTIO DD Package 8-Lead Plastic DFN (3mm
×
3mm)
(Reference LTC DWG # 05-08-1698) R = 0.115 0.38 ± 0.10 TYP 5 8 0.675 ±0.05 3.00 ±0.10 1.65 ± 0.10 3.5 ±0.05 1.65 ±0.05 (4 SIDES) (2 SIDES) 2.15 ±0.05 (2 SIDES) PIN 1 TOP MARK PACKAGE (NOTE 6) OUTLINE 4 1 0.200 REF 0.75 ±0.05 0.25 ± 0.05 0.25 ± 0.05 0.50 BSC 0.50 2.38 ±0.10 BSC (2 SIDES) 0.00 – 0.05 2.38 ±0.05 BOTTOM VIEW—EXPOSED PAD (2 SIDES) NOTE: RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) (DD) DFN 1203 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 20512fd 9