LT3991/LT3991-3.3/LT3991-5 pin FuncTionsPG (Pin 9): The PG pin is the open-drain output of an at low output loads. Tie to a clock source for synchroni- internal comparator. PGOOD remains low until the FB pin zation, which will include pulse-skipping at low output is within 9% of the final regulation voltage. PGOOD is loads. When in pulse-skipping mode, quiescent current valid when the LT3991 is enabled and VIN is above 4.3V. increases to 1.5mA. SYNC (Pin 10): This is the external clock synchronization GND (Exposed Pad Pin 11): Ground. The exposed pad input. Ground this pin for low ripple Burst Mode operation must be soldered to PCB. block DiagraM VIN VIN – C1 INTERNAL 1.19V REF + BD 1V + SWITCH Σ SLOPE COMP LATCH – SHDN EN BOOST R OSCILLATOR C3 Q 200kHz TO 2MHz RT R S L1 T VOUT SW Burst Mode SYNC DETECT D1 C2 PG ERROR AMP V + 1.09V + C CLAMP VC 1µA – – SS C4 SHDN C5 LT3991-3.3 LT3991-5 ONLY R2 R1 GND FB LT3991 VOUT ONLY R2 R1 3991 BD C5 3991fa 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Related Parts
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