Datasheet LTC3824 (Analog Devices) - 8

LTC3824
block DiagraM
SENSE + VCC + VIN Burst Mode 1.1V – SS DISABLE REFERENCE RS 100k VREF GATE B1 Q1 C 1.8V 2.5V + CAP 0.1µF L 8V 250k VOUT 0.3µA 100k SYNC/ – Q MODE C2 + Y1 S R RF1 – + – + CAP M2 + D1 50pF + COUT – 1 E1 2V + M1 1.5V RF2 OR1 RSET OSC + + 50KHz FOLDBACK + 0.5V Y2 – SYNC DISABLE Y5 – + RFREQ 6 0.1V SLOPE + COMP + + + SHUTDOWN Y6 – 0.025V + FB D6 GND PWM – – GM D7 VREF Burst Mode + 0.8V OPERATION CONTROL D4 5µA 2.5V VC SS R1 2k 3824 BD C1 CSS 470pF 0.1µF
applicaTions inForMaTion Operation
In normal operation each switching cycle starts with switch The LTC3824 is a constant frequency current mode buck turn-on and the inductor current is sampled through the controller with programmable switching frequency up to current sense resistor. This current is amplified and then 600kHz. compared to the error amplifier output VC to turn the switch off. Voltage loop regulates the output voltage to Referring to the Block Diagram, the LTC3824’s basic the programmed level through the output resistor divider functions include a transconductance amplifier gm to and the error amplifier. Amplifier E1 regulates the gate regulate the output voltage and control the current mode drive low to approximately 8V below VCC for VCC higher PWM current loop, the necessary logic to control the than 9V, and CCAP stabilizes the voltage. Note that when PWM switching cycles, a high speed gate driver to drive VCC is lower than 9V, gate drive high will be within 0.5V an external high power P-channel MOSFET and a voltage of VCC and gate drive low within 1V of ground. regulator to bias the gate driver circuit. Important features include shutdown, current limit, soft- start, synchronization and low quiescent current. 3824fh 8 For more information www.linear.com/LTC3824 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Typical Performance Characteristics Applications Information Typical Application Related Parts