LT1766/LT1766-5 BLOCK DIAGRAM will have 90° phase shift at a much lower frequency, but output voltage). This will improve effi ciency if the BIAS will not have the additional 90° shift until well beyond pin voltage is lower than regulator input voltage. the LC resonant frequency. This makes it much easier to High switch effi ciency is attained by using the BOOST frequency compensate the feedback loop and also gives pin to provide a voltage to the switch driver which is much quicker transient response. higher than the input voltage, allowing switch to be satu- Most of the circuitry of the LT1766 operates from an internal rated. This boosted voltage is generated with an external 2.9V bias line. The bias regulator normally draws power capacitor and diode. Two comparators are connected to the from the regulator input pin, but if the BIAS pin is connected shutdown pin. One has a 2.38V threshold for undervoltage to an external voltage higher than 3V, bias power will be lockout and the second has a 0.4V threshold for complete drawn from the external source (typically the regulated shutdown. VIN 4 RLIMIT RSENSE 2.9V BIAS INTERNAL + – BIAS 10 REGULATOR VCC CURRENT COMPARATOR SLOPE COMP ∑ SYNC 14 ANTISLOPE COMP BOOST 6 SHUTDOWN COMPARATOR + – 200kHz S OSCILLATOR Q1 RS DRIVER POWER FLIP-FLOP CIRCUITRY SWITCH R 0.4V 5.5μA 2 SW SHDN 15 + FREQUENCY – FOLDBACK LOCKOUT COMPARATOR ×1 Q2 FOLDBACK VC(MAX) Q3 CURRENT CLAMP LIMIT ERROR CLAMP AMPLIFIER – 12 FB gm = 2000μMho + 11 2.38V 1.22V VC GND 1, 8, 9, 16, 17 1766 F01 Figure 1. LT1766 Block Diagram 1766fc 9
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