Datasheet IRF5210SPbF, IRF5210LPbF (Infineon) - 7

IRF5210S/LPbF
Peak Diode Recovery dv/dt Test Circuit D.U.T
* Circuit Layout Considerations + • Low Stray Inductance ƒ • Ground Plane • Low Leakage Inductance Current Transformer - + ‚ „ - + -  + RG • dv/dt controlled by RG - • ISD controlled by Duty Factor "D" VDD • D.U.T. - Device Under Test VGS * Reverse Polarity of D.U.T for P-Channel Driver Gate Drive P.W. Period D = P.W. Period [ ] *** VGS=10V D.U.T. ISD Waveform Reverse Recovery Body Diode Forward Current Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD [ ] Re-Applied Voltage Body Diode Forward Drop Inductor Curent Ripple ≤ 5% ISD [ ] *** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 15.
For P-Channel HEXFETS www.irf.com 7