Datasheet IRF4905SPbF, IRF4905LPbF (Infineon) - 8

IRF4905S/L Driver Gate Drive P.W. Period D =
D.U.T
** P.W. Period + V * ƒ Circuit Layout Considerations GS=10V • Low Stray Inductance • Ground Plane - • Low Leakage Inductance D.U.T. I Current Transformer SD Waveform + Reverse ‚ Recovery Body Diode Forward „ Current Current - + - di/dt D.U.T. VDS Waveform Diode Recovery dv/dt  VDD • dv/dt controlled by R VDD Re-Applied RG G + Voltage • Driver same type as D.U.T. Body Diode Forward Drop • ISD controlled by Duty Factor "D" - Inductor Curent • D.U.T. - Device Under Test Ripple ≤ 5% ISD ** Reverse Polarity of D.U.T for P-Channel * VGS = 5V for Logic Level Devices
Fig 17.
Peak Diode Recovery dv/dt Test Circuit for P-Channel HEXFET® Power MOSFETs RD VDS VGS D.U.T. RG -+ VDD VGS Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
Fig 18a.
Switching Time Test Circuit td(on) tr td(off) tf VGS 10% 90% VDS
Fig 18b.
Switching Time Waveforms 8 www.irf.com