Datasheet LTC6412 (Analog Devices) - 3

LTC6412
DC ELECTRICAL CHARACTERISTICS The
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denotes specifi cations that apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. DC electrical performance measured using DC test circuit schematic. VIN(DIFF) is defi ned as (+IN) – (–IN). VOUT(DIFF) is defi ned as (+OUT) – (–OUT). VIN(CM) is defi ned as [(+IN) + (–IN)]/2. VOUT(CM) is defi ned as [(+OUT) + (–OUT)]/2. Unless noted otherwise, default operating conditions are VCC = 3.3V, EN = 0.8V, SHDN = 2.2V, +VG tied to VREF (negative gain slope mode), VOUT(CM) = 3.3V. Differential power gain defi ned at ZSOURCE = 50Ω differential and ZLOAD = 200Ω differential. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Gain Characteristics
GMAX Maximum Differential Power Gain (Note 4) –VG = 0V, VIN(DIFF) = 100mV 16.1 17.1 18.1 dB l 15.5 18.7 dB GMIN Minimum Differential Power Gain (Note 4) –VG = 1.2V, VIN(DIFF) = 200mV –16.2 –14.9 –13.6 dB l –16.8 –13.0 dB GRANGE Differential Power Gain Range GMAX-GMIN 30.7 31.9 33.1 dB l 30.1 33.7 dB TCGAIN Temperature Coeffi cient of Gain at Fixed VG –VG = 0V to 1.2V –0.007 dB/°C GSLOPE Gain Control Slope –VG = 0.2V to 1.0V, 85 Points, Slope of the –34.1 –32.9 –31.7 dB/V Least-Square Fit Line l –34.7 –31.1 dB/V GCONF(AVE) Average Conformance Error to Gain Slope Line –VG = 0.2V to 1.0V, 85 Points, Standard 0.12 0.20 dB Error to the Least-Square Fit Line GCONF(MAX) Maximum Conformance Error to Gain Slope –VG = 0.2V to 1.0V, 85 points, Maximum 0.20 0.45 dB Line Error to the Least-Square Fit Line
+IN and –IN Pins
RIN(GMAX) Differential Input Resistance at Maximum Gain –VG = 0V, VIN(DIFF) = 100mV 49 57 65 Ω l 47 67 Ω RIN(GMIN) Differential Input Resistance at Minimum Gain –VG = 1.2V, VIN(DIFF) = 200mV 49 57 65 Ω l 47 67 Ω VINCM(GMAX) Input Common Mode Voltage at Maximum Gain –VG = 0V, DC Blocking Capacitor to Input 640 mV VINCM(GMIN) Input Common Mode Voltage at Minimum Gain –VG = 1.2V, DC Blocking Capacitor to Input 640 mV
+VG, –VG, and VREF Pins
RIH(+VG) +VG Input High Resistance +VG = 1.0V, –VG Tied to VREF , 7.8 9.2 10.6 kΩ RIN(+VG) = 1V/Δ IIL(+VG) l 7.2 11.6 kΩ RIH(–VG) –VG Input High Resistance –VG = 1.0V, +VG Tied to VREF , 7.8 9.2 10.6 kΩ RIN(–VG) = 1V/Δ IIL(–VG) l 7.2 11.6 kΩ IIL(+VG) +VG Input Low Current +VG = 0V, –VG Tied to VREF –9 –5 –1 μA l –10 –1 μA IIL(–VG) –VG Input Low Current –VG = 0V, +VG Tied to VREF –9 –5 –1 μA l –10 –1 μA VREF Internal Bias Voltage –VG = 0V, +VG Tied to VREF 590 615 640 mV l 580 650 mV 6412fa 3