Datasheet AD8376 (Analog Devices) - 6

AD8376 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A A A+ A– A+ A– ND CC P P A1 A0 PI PI G V O O 32 31 30 29 28 27 26 25 A2 1 24 OPA+ PIN 1 A3 2 23 OPA– INDICATOR A4 3 22 ENBA VCMA 4 AD8376 21 GNDA VCMB 5 TOP VIEW 20 GNDB B4 6 (Not to Scale) 19 ENBB B3 7 18 OPB– B2 8 17 OPB+ 9 1 10 1 12 13 14 15 16 – B1 B0 B+ B– B+ B
002
PI PI NDB CCB P G V O OP
06725-
NOTES 1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO GROUND. SOLDER TO A LOW IMPEDANCE GROUND PLANE.
Figure 3. 32-Lead LFCSP
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 A2 MSB − 2 for the Gain Control Interface for Channel A. 2 A3 MSB − 1 for the Gain Control Interface for Channel A. 3 A4 MSB for the 5-Bit Gain Control Interface for Channel A. 4 VCMA Channel A Input Common-Mode Voltage. Typically bypassed to ground through capacitor. 5 VCMB Channel B Input Common-Mode Voltage. Typically bypassed to ground through capacitor. 6 B4 MSB for the 5-Bit Gain Control Interface for Channel B. 7 B3 MSB − 1 for the Gain Control Interface for Channel B. 8 B2 MSB − 2 for the Gain Control Interface for Channel B. 9 B1 LSB + 1 for the Gain Control Interface for Channel B. 10 B0 LSB for the Gain Control Interface for Channel B. 11 IPB+ Channel B Positive Input. 12 IPB− Channel B Negative Input. 13, 20 GNDB Device Common (DC Ground) for Channel B. 14 VCCB Positive Supply Pin for Channel B. Should be bypassed to ground using suitable bypass capacitor. 15, 17 OPB+ Positive Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal. 16, 18 OPB− Negative Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal. 19 ENBB Power Enable Pin for Channel B. Channel B is enabled with a logic high and disabled with a logic low. 21, 28 GNDA Device Common (DC Ground) for Channel A. 22 ENBA Power Enable Pin for Channel A. Channel A is enabled with a logic high and disabled with a logic low. 23, 25 OPA− Negative Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal. 24, 26 OPA+ Positive Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal. 27 VCCA Positive Supply Pins for Channel A. Should be bypassed to ground using suitable bypass capacitor. 29 IPA− Channel A Negative Input. 30 IPA+ Channel A Positive Input. 31 A0 LSB for the Gain Control Interface for Channel A. 32 A1 LSB + 1 for the Gain Control Interface for Channel A. Exposed Pad Internally connected to ground. Solder to a low impedance ground plane. Rev. B | Page 6 of 24 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Circuit Description Basic Structure Input System Output Amplifier Gain Control Applications Basic Connections Single-Ended-to-Differential Conversion Broadband Operation ADC Interfacing Layout Considerations Characterization Test Circuits Differential-to-Differential Characterization Evaluation Board Outline Dimensions Ordering Guide