Datasheet LTC6800 (Analog Devices) - 9

LTC6800 applicaTions inForMaTion UNITY GAIN UNITY GAIN NONUNITY GAIN NONUNITY GAIN 5V 5V 5V 5V 8 8 8 8 3 3 3 3 V+IN + V+IN + + + V+IN + V+IN + 7 7 + 7 + 7 VIN VOUT V VOUT V VOUT V VOUT – IN 2 6 –IN IN 2 6 – 2 6 R2 – 2 6 R2 V–IN – 5 V–IN – 5 V–IN – 5 V–IN – 5 4 4 4 R1 4 R1 VREF VREF VREF 0V < V+IN < 5V 0V < V–IN < 5V AND |V–IN – VREF| < 5.5V 0V < V–IN < 5V AND |V–IN – VREF| < 5.5V 0V < V–IN < 5V AND |V–IN – VREF| < 5.5V 0V < V–IN < 5V 0V < V+IN < 5V AND |V+IN – VREF| < 5.5V 0V < V+IN < 5V AND |V+IN – VREF| < 5.5V 0V < V+IN < 5V AND |V+IN – VREF| < 5.5V 0V < VIN < 3.7V 0V < VIN + VREF < 3.7V 0V < VIN + VREF < 3.7V 0V < VIN + VREF < 3.7V VOUT = VIN R2 R2 V OUT = VIN + VREF V OUT = 1 + VIN + VREF VOUT = 1 + (VIN + VREF) R1 R1 6800 F01
Figure 1 Input Current
In the Typical Performance Characteristics section of this Whenever the differential input V data sheet, there are curves showing the additional error IN changes, CH must be charged up to the new input voltage via C from nonzero source resistance in the inputs. If there are S. This results in an input charging current during each input sampling no large capacitors across the inputs, the amplifier is period. Eventually, C less sensitive to source resistance and source resistance H and CS will reach VIN and, ideally, the input current would go to zero for DC inputs. mismatch. When large capacitors are placed across the inputs, the input charging currents previously described In reality, there are additional parasitic capacitors which result in larger DC errors, especially with source resistor disturb the charge on CS every cycle even if VIN is a DC mismatches. voltage. For example, the parasitic bottom plate capacitor on CS must be charged from the voltage on the REF pin
Power Supply Bypassing
to the voltage on the –IN pin every cycle. The resulting The LTC6800 uses a sampled data technique and, therefore, input charging current decays exponentially during each contains some clocked digital circuitry. It is, therefore, input sampling period with a time constant equal to RSCS. sensitive to supply bypassing. A 0.1µF ceramic capacitor
If the voltage disturbance due to these currents settles
must be connected between Pin 8 (V+) and Pin 4 (V–) with
before the end of the sampling period, there will be no
leads as short as possible.
errors due to source resistance or the source resistance mismatch between –IN and +IN. With RS less than 10k, no DC errors occur due to this input current.
6800fb Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts Typical Application